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Nanoscale memristive devices for memory and logic applications.

机译：用于存储器和逻辑应用的纳米级忆阻器件。

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摘要

As the building block of semiconductor electronics, field effect transistor (FET), approaches the sub 100 nm regime, a number of fundamental and practical issues start to emerge such as short channel effects that prevent the FET from operating properly and sub-threshold slope non-scaling that leads to increased power dissipation. In terms of nonvolatile memory, it is generally believed that transistor based Flash memory will approach the end of scaling within about a decade. As a result, novel, non-FET based devices and architectures will likely be needed to satisfy the growing demands for high performance memory and logic electronics applications.;In this thesis, we present studies on nanoscale resistance switching devices (memristive devices). The device shows excellent resistance switching properties such as fast switching time (50 ns), high on/off ratio (>10 6), good data retention (>6 years) and programming endurance (>10 5). The studies suggest that the nonvolatile resistance switching in a nanoscale a-Si resistive switch is caused by the formation of a single conductive filament within 10 nm range near the bottom electrode. New functionalities, such as multi-bit switching with partially formed filaments, can be obtained by controlling the resistance switching process through current programming. As digital memory devices, the devices are ideally suited in the crossbar architecture which offers ultra-high density and intrinsic defect tolerance capability. As an example, a high-density (2 Gbits/cm2) lkb crossbar memory was demonstrated with excellent uniformity, high yield (>92%) and ON/OFF ratio (>103), proving its promising aspects for memory and reconfigurable logic applications.;Furthermore, we demonstrated that properly designed devices can exhibit controlled analog switching behavior and function as flux controlled memristor devices. The analog memristors can be used in biology-inspired neuromorphic circuits in which signal processing efficiency orders of magnitude higher than conventional digital computer systems can be reached. As a prototype illustration, we showed Spike Timing Dependent Plasticity (STDP), one of the key learning rules in biological system, can be realized by CMOS neurons and nanoscale memristor synapses.
机译：随着半导体电子器件场效应晶体管（FET）接近100 nm以下，许多基本和实际问题开始出现，例如短沟道效应会阻止FET正常运行，并且亚阈值斜率会降低。缩放会导致功耗增加。就非易失性存储器而言，通常认为基于晶体管的闪存将在大约十年内接近缩放的极限。结果，可能需要新颖的，非基于FET的器件和架构来满足对高性能存储器和逻辑电子应用的不断增长的需求。在本文中，我们对纳米级电阻开关器件（忆阻器件）进行了研究。该器件具有出色的电阻切换特性，例如快速的切换时间（<50 ns），高的开/关比（> 10 6），良好的数据保持能力（> 6年）和编程耐久性（> 10 5）。研究表明，纳米级a-Si电阻开关中的非易失性电阻开关是由在底部电极附近10 nm范围内形成单个导电丝引起的。通过电流编程控制电阻切换过程，可以获得新功能，例如具有部分形成细丝的多位切换。作为数字存储设备，这些设备非常适合交叉开关架构，该架构具有超高密度和固有的缺陷容忍能力。例如，高密度（2 Gbits / cm2）lkb交叉开关存储器具有出色的均匀性，高良率（> 92％）和开/关比（> 103），证明了其在存储器和可重构逻辑应用方面的广阔前景此外，我们证明了设计合理的器件可以表现出受控的模拟开关性能，并可以作为通量受控的忆阻器器件。模拟忆阻器可用于受生物启发的神经形态电路，在这种电路中，信号处理效率可达到比传统数字计算机系统高几个数量级的水平。作为原型说明，我们展示了Spike时序依赖可塑性（STDP），这是生物系统中的关键学习规则之一，可以通过CMOS神经元和纳米级忆阻器突触来实现。

著录项

  • 作者

    Jo, Sung Hyun.;

  • 作者单位

    University of Michigan.;

  • 授予单位 University of Michigan.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2010
  • 页码 143 p.
  • 总页数 143
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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