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Cell Based Synthesized Low Noise All Digital Frequency Synthesizer, 0.13mum CMOS and FPGA Implementations.

机译：基于单元的合成低噪声全数字频率合成器，0.13mum CMOS和FPGA实现。

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This thesis proposed an all digital phase locked loop (ADPLL) that consists of a Bang-Bang phase frequency detector (BBPFD) without any cycle-slip and with a narrow dead-zone, a digitally controlled oscillator (DCO) with a built-in low pass filter (LPF), and a multi-modulus divider (MMD) with an extended divide range The loop dynamics and phase noise is simulated by the behavioral simulation in SystemVerilog. The proposed ADPLL is fully synthesized in the field programmable gate array (FPGA) as a fast prototype and is also implemented in 0.13µm complementary metal-oxide semiconductor (CMOS) technology by the standard digital cells and two custom high speed cells. The measured open-loop and closed-loop phase noise of the fabricated CMOS ADPLL are –123.10dBc/Hz and –120.77 dBc/Hz both at 1MHz offset of a carrier of 1.35 GHz.

机译：本文提出了一种全数字锁相环（ADPLL），它由一个无周期跳变且死区较窄的Bang-Bang鉴频鉴相器（BBPFD），一个内置的数控振荡器（DCO）组成。低通滤波器（LPF）和具有扩展分频范围的多模分频器（MMD）通过 SystemVerilog 中的行为模拟来模拟环路动态和相位噪声。拟议的ADPLL作为快速原型完全集成在现场可编程门阵列（FPGA）中，并由标准数字单元和两个定制高速单元以0.13µm互补金属氧化物半导体（CMOS）技术实现。在1 MHz <时，所制造的CMOS ADPLL测得的开环和闭环相位噪声均为–123.10 dBc / Hz 和–120.77 dBc / Hz 。 / italic> 1.35 GHz 载波的偏移。

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作者
Wen, Tingjun.;
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作者单位

Carleton University (Canada).;

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授予单位 Carleton University (Canada).;
学科 Engineering Electronics and Electrical.
学位 M.A.Sc.
年度 2011
页码 104 p.
总页数 104
原文格式 PDF
正文语种 eng
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1. A Low-Noise Wide-BW 3.6-GHz Digital $DeltaSigma$ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation [J] . Hsu C.-H., Straayer M. Z., Perrott M. H. IEEE Journal of Solid-State Circuits . 2008,第12期

机译：具有降噪时间数字转换器和量化噪声消除功能的低噪声宽带宽3.6GHz数字$ DeltaSigma $小数N频率合成器
2. A Fully Integrated 0.13- $mu$m CMOS Digital Low-IF DBS Satellite Tuner Using a Ring Oscillator-Based Frequency Synthesizer [J] . Adrian Maxim, Ramin K. Poorfard, Richard A. Johnson, IEEE Journal of Solid-State Circuits . 2007,第期

机译：使用基于环形振荡器的频率合成器完全集成的0.13-μmCMOS数字低中频DBS卫星调谐器
3. A Fully Integrated 0.13- $mu$m CMOS Digital Low-IF DBS Satellite Tuner Using a Ring Oscillator-Based Frequency Synthesizer [J] . Maxim A., Poorfard R. K., Johnson R. A., IEEE Journal of Solid-State Circuits . 2007,第5期

机译：使用基于环形振荡器的频率合成器完全集成的0.13-μmCMOS数字低中频DBS卫星调谐器
4. A low-noise, 8.95–11GHz all-digital frequency synthesizer with a metastability-free time-to-digital converter and a sleepy counter in 65nm CMOS [C] . Jiang Chen, Liu Junren, Huang Yumei, 2012 Proceedings of the ESSCIRC. . 2012

机译：低噪声，8.95-11GHz全数字频率合成器，具有无亚稳态的时间数字转换器和65nm CMOS的休眠计数器
5. Low-phase-noise, low-timing-jitter design techniques for delay cell based VCOs and frequency synthesizers. [D] . Weigandt, Todd Charles. 1998

机译：用于基于延迟单元的VCO和频率合成器的低相位噪声，低时序抖动设计技术。
6. Efficient Smart CMOS Camera Based on FPGAs Oriented to Embedded Image Processing [O] . Ignacio Bravo, Javier Baliñas, Alfredo Gardel, 2011

机译：基于面向嵌入式图像处理的FPGA的高效智能CMOS相机
7. Cell based synthesized low noise all digital frequency synthesizer, 0.13μm CMOS and FPGA implementations [O] . Tingjun Wen -1

机译：基于单元的合成低噪声所有数字频率合成器，0.13μmCMOS和FPGA实现

Cell Based Synthesized Low Noise All Digital Frequency Synthesizer, 0.13mum CMOS and FPGA Implementations.

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