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Solving complex modeling of system-on-a-chip (SOC) test automation and optimal resource allocation by neural networks.

机译：通过神经网络解决复杂的系统级芯片（SOC）测试自动化建模和最佳资源分配问题。

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摘要

In this research, we investigate the methods for solving the complex modeling of System-on-a-Chip (SOC) test automation. In the semiconductor industry, a new system design, called System-on-a-Chip (SOC) design, is currently being introduced to use multiple embedded modules built on a single chip. With today's technology, a single chip can consist of millions of transistors or components. To design a SOC system on a single chip, a designer often uses pre-designed, reusable megacells known as cores in the SOC design. Embedded the cores onto SOC increases width of the system bus and thus increases overall system performance, i.e., it can offer higher speed and lower power consumption on SOC chips.; The objective of this research is to optimize the testing time and the test resource allocation for System-on-a-Chip (SOC). The mathematic formulation and the neural networks with different techniques are proposed to solve these SOC test problems. The objective of this SOC test automation is to minimize the SOC testing time subject to different constraints: (i) precedence constraint, (ii) test resource constraint, (iii) core constraint, and (iv) power constraint. Heuristic algorithms are used to help the neural network avoid getting trapped in a local optimal. The developed neural networks can effectively solve the SOC test scheduling models with disjunctive constraints. The proposed maximum neural network can be used to solve NP-hard SOC test problems within polynomial time. The results show that it is possible to find the optimal SOC testing time of the complex SOC systems with shorter computation time than the existing traditional methods. The techniques presented in this research can be used in the test automation for System-on-a-Chip (SOC) design.
机译：在这项研究中，我们研究解决片上系统（SOC）测试自动化的复杂建模的方法。在半导体行业，目前正在引入一种称为片上系统（SOC）设计的新系统设计，以使用在单个芯片上构建的多个嵌入式模块。利用当今的技术，单个芯片可以包含数百万个晶体管或组件。为了在单个芯片上设计SOC系统，设计人员通常使用预先设计的可重复使用的巨型电池，在SOC设计中称为 core 。将内核嵌入到SOC中可以增加系统总线的宽度，从而提高整体系统性能，即，可以在SOC芯片上提供更高的速度和更低的功耗。这项研究的目的是优化片上系统（SOC）的测试时间和测试资源分配。为了解决这些SOC测试问题，提出了采用不同技术的数学公式和神经网络。此SOC测试自动化的目标是最大程度地减少受到不同约束的SOC测试时间：（i）优先约束，（ii）测试资源约束，（iii）核心约束和（iv）功率约束）。启发式算法用于帮助神经网络避免陷入局部最优状态。所开发的神经网络可以有效地解决具有分离约束的SOC测试调度模型。所提出的最大神经网络可用于解决多项式时间内的NP-hard SOC测试问题。结果表明，与现有的传统方法相比，可以以更短的计算时间找到复杂SOC系统的最优SOC测试时间。这项研究中介绍的技术可以用于片上系统（SOC）设计的测试自动化中。

著录项

  • 作者

    Kloypayan, Jirawan.;

  • 作者单位

    North Carolina State University.;

  • 授予单位 North Carolina State University.;
  • 学科 Engineering Industrial.
  • 学位 Ph.D.
  • 年度 2002
  • 页码 101 p.
  • 总页数 101
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 一般工业技术;
  • 关键词

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