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Residue number system arithmetic logic unit (ALU) with general division based on a new technique in moduli set selection.

机译：基于模集选择新技术的通用除数系统算术逻辑单元（ALU）。

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Residue Number System (RNS) offers a promising future for highly parallel computing hardware because its carry-free operations in addition, subtraction and multiplication. However, unless the problems with its complex sign detection, number comparison, and division are solved, general computing RNS will not be reality. This dissertation work offers a solution to that problem and presents a prototype of RNS arithmetic logic unit (ALU), which is also capable to perform general division.; With the new technique in selecting moduli set proposed in this work, one can find a moduli set with any number of modulus, which can simplify sign detection in RNS. This, in turn, can improve the performance of number comparison, and with this progress, division in RNS can be done easily and fast.; The prototype of the ALU was implemented in two ICs, namely AU1 and AU2, based on moduli set {lcub}31, 15, 2{rcub}. AU1 is capable of performing RNS addition, subtraction and number comparison. The inputs to this IC are two RNS numbers, a 2-bit opcode, and clock. The outputs are one RNS number, which shows the result of the addition/subtraction 2-bit output for comparison results, and 3 status flags for zero, negative and overflow. The second chip, AU2, can perform RNS multiplication and division. The inputs to this IC are two RNS numbers, a 1-bit opcode, and clock. The outputs are one RNS number, which shows the product of the multiplication or the quotient of the division, and a status flag indicating the validity of the result.; All of the designs in this work were carried out in VHDL (Very-High-Speed-IC Hardware Description Language). The simulation and physical layout of the ICs were done using EDA software from Mentor Graphics, which includes Modelsim, Leonardo Spectrum, Quickpath, Quicksim, and IC Station.
机译：残数系统（RNS）为高度并行的计算硬件提供了一个有希望的未来，因为它的加，减，乘运算操作自由。但是，除非解决了其复杂的符号检测，数字比较和除法问题，否则通用计算RNS将不会成为现实。本文的工作为该问题提供了解决方案，并提出了RNS算术逻辑单元（ALU）的原型，该原型也能够执行一般的除法。利用这项工作中提出的选择模数集的新技术，可以找到具有任意数量模数的模数集，从而可以简化RNS中的符号检测。反过来，这可以提高数字比较的性能，并且随着这一进展，可以轻松，快速地完成RNS中的划分。基于模数集{lcub} 31、15、2 {rcub}，ALU的原型在两个IC中实现，即AU1和AU2。 AU1能够执行RNS加，减和数字比较。该IC的输入是两个RNS编号，一个2位操作码和一个时钟。输出是一个RNS编号，该数字显示用于比较结果的加/减2位输出的结果，以及用于零，负和溢出的3个状态标志。第二个芯片AU2可以执行RNS乘法和除法。该IC的输入是两个RNS编号，一个1位操作码和一个时钟。输出是一个RNS编号，表示乘积或除数的乘积，以及一个状态标志，指示结果的有效性。这项工作中的所有设计均以VHDL（超高速IC硬件描述语言）进行。 IC的仿真和物理布局是使用Mentor Graphics的EDA软件完成的，其中包括Modelsim，Leonardo Spectrum，Quickpath，Quicksim和IC Station。

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