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A 2.4 GHz, low power, fully-integrated CMOS frequency synthesizer for wireless communications.

机译：一种用于无线通信的2.4 GHz低功耗，完全集成的CMOS频率合成器。

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摘要

A low phase noise/spur, high switching speed frequency synthesizer, which features a low power consumption, a high level of integration, and a low cost is highly desirable for wireless communications. A conventional type-II charge pump PLL frequency synthesizer typically has a relatively slow switching speed. The continuous time RC loop filter is sensitive to process and temperature variations.; A type-I charge pump PLL frequency synthesizer is proposed in this work. The stabilization of the closed loop system is achieved by using a discrete-time loop filter. The type-I system architecture leads to fast switching speed. The discrete time loop filter provides isolation between the phase/frequency detector and the VCO tuning node. Hence a good spur performance can be achieved. The proposed PLL frequency synthesizer is more suitable for integration.; To demonstrate the performance of the proposed type-I charge pump PLL frequency synthesizer architecture, a prototype 2.4GHz frequency synthesizer for the Bluetooth standard was developed. Design, analysis and extensive simulations were carried out at both system level and circuit level. The test chip was fabricated in a 0.25um CMOS process. The measurement results of the prototype PLL frequency synthesizer verified the principle of the proposed architecture. A switching time of 30us and a reference spur of −62dBc were achieved.; Compared with the state-of-the-art CMOS frequency synthesizer based on conventional type-II charge pump PLL frequency synthesizer architecture for the same Bluetooth application reported in [3], the switching speed of the prototype type-I charge pump PLL frequency synthesizer is about five times faster than that of the conventional frequency synthesizer. The reference spur performance of the prototype is 9dB better than that of conventional frequency synthesizer. The phase noise of the prototype at 550kHz offset and 2MHz offset are 1dB better and 10 dB better than that of the conventional frequency synthesizer, respectively. A typical conventional frequency synthesizer [3] has an off-chip continuous time loop filter. The prototype features a discrete time on-chip loop filter except one off-chip capacitor for testing purpose, which could be integrated. In conclusion, the prototype type-I charge pump frequency synthesizer achieves a much better overall performance than the conventional CMOS type-II charge pump PLL frequency synthesizer.
机译：无线通信非常需要具有低功耗，高集成度和低成本的低相位噪声/杂散，高开关速度频率合成器。常规的II型电荷泵PLL频率合成器通常具有相对较慢的开关速度。连续时间RC环路滤波器对过程和温度变化敏感。这项工作提出了一种I型电荷泵PLL频率合成器。闭环系统的稳定是通过使用离散时间环路滤波器实现的。 I型系统架构可实现快速切换速度。离散时间环路滤波器在相位/频率检测器和VCO调谐节点之间提供隔离。因此，可以实现良好的支线性能。所提出的PLL频率合成器更适合集成。为了演示建议的I型电荷泵PLL频率合成器架构的性能，开发了用于蓝牙标准的原型2.4GHz频率合成器。在系统级和电路级都进行了设计，分析和广泛的仿真。测试芯片采用0.25um CMOS工艺制造。原型PLL频率合成器的测量结果验证了所提出架构的原理。开关时间为30us，基准杂散为-62dBc。与[3]中报道的基于相同蓝牙应用的基于常规II型电荷泵PLL频率合成器架构的最新CMOS频率合成器相比，原型I型电荷泵PLL频率合成器的开关速度比传统的频率合成器快约五倍。原型的基准杂散性能比常规频率合成器好9dB。原型在550kHz偏移和2MHz偏移下的相位噪声分别比常规频率合成器好1dB和10dB。典型的常规频率合成器[3]具有片外连续时间环路滤波器。该原型具有一个离散时间片上环路滤波器，除了一个用于测试目的的片外电容器外，该电容器可以集成。总之，与传统的CMOS II型电荷泵PLL频率合成器相比，原型I型电荷泵频率合成器具有更好的整体性能。

著录项

  • 作者

    Zhang, Benyong.;

  • 作者单位

    Georgia Institute of Technology.;

  • 授予单位 Georgia Institute of Technology.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2001
  • 页码 165 p.
  • 总页数 165
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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