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A 100 MHz 6th Order Continuous Time Band-Pass Sigma Delta Modulator with Active Inductor Resonators.

机译：具有有源电感谐振器的100 MHz六阶连续时间带通Sigma Delta调制器。

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摘要

Band-Pass Sigma Delta Modulators allow for the digitization of a carrier signal directly without frequency down conversion to baseband. This results in a simpler and more economical RF receiver front end. The holy grail of signal processing is to develop a Band-Pass Analog to Digital Converter operating at a high enough frequency to digitize high frequency RF signals such as Wi-Fi or cell phone carriers without the need for complicated Filters, Mixers and Amplifiers in the receiver front end.;Continuous Time Band-Pass Sigma Delta Analog to Digital Converters are potentially one technology that can be used to realize this goal because of their ability to operate at higher frequencies than their switched capacitor counterparts. Current Continuous Time Band-Pass Sigma Delta Modulators utilize LC circuits as resonators. This leads to a design that occupies a large die area. In fact, in many designs the area of the spiral inductors occupies more than half the design area. Another drawback of using spiral inductors is the limited quality factor. In order for there to be a high dynamic range at the output of a sigma delta modulator it is necessary to have resonators with high quality factors. We investigate the effects of replacing spiral inductors with high quality factor active inductor resonators with negative impedance circuits.;CMOS is a fairly cheap technology when compared to other ASIC design technologies. It also offers lower power consumption but its operating frequencies are somewhat lower. We have chosen to use CMOS technology for our design because of its economy and low power consumption. We have been able to design and simulate a 6th order, continuous time Band-Pass Sigma Delta modulator in IBM 0.18u cmrf7sf CMOS technology. Cadence schematic simulations show a modulator with a high dynamic range and decreased area usage.;Pad to pad simulation of the extracted layout in Cadence yields an enhanced peak SNDR of 73 dB with a noise bandwidth of 36 kHz and a power consumption of 12 mW. This modulator occupies 2.05 mm2 of active die area.
机译：带通Sigma Delta调制器可直接将载波信号数字化，而无需下变频到基带。这导致更简单，更经济的RF接收器前端。信号处理的圣杯是开发以足够高的频率工作的带通模数转换器，以数字化高频RF信号（例如Wi-Fi或手机载波），而无需在其中使用复杂的滤波器，混频器和放大器。连续时间带通Sigma Delta模数转换器潜在地是一项可用于实现该目标的技术，因为它们能够以比开关电容器同类产品更高的频率工作。当前的连续时间带通Sigma Delta调制器利用LC电路作为谐振器。这导致占据较大芯片面积的设计。实际上，在许多设计中，螺旋电感器的面积占设计面积的一半以上。使用螺旋电感器的另一个缺点是有限的品质因数。为了在Σ-Δ调制器的输出处具有高动态范围，必须具有高质量因子的谐振器。我们研究了用具有负阻抗电路的高品质因数有源电感谐振器替代螺旋电感器的效果。与其他ASIC设计技术相比，CMOS是一种相当便宜的技术。它还具有较低的功耗，但其工作频率较低。由于其经济性和低功耗，我们选择在设计中使用CMOS技术。我们已经能够使用IBM 0.18u cmrf7sf CMOS技术设计和仿真6阶连续时间带通Sigma Delta调制器。 Cadence的原理图仿真显示了一个具有高动态范围和减少的面积使用的调制器。在Cadence中对提取的布局进行逐个焊盘仿真可产生73 dB的增强SNDR峰值，噪声带宽为36 kHz，功耗为12 mW。该调制器占据2.05 mm2的有源芯片面积。

著录项

  • 作者

    Dobson, Kevin.;

  • 作者单位

    The George Washington University.;

  • 授予单位 The George Washington University.;
  • 学科 Electrical engineering.;Computer engineering.
  • 学位 Ph.D.
  • 年度 2016
  • 页码 115 p.
  • 总页数 115
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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