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A deep submicron drain-current and charge model for MOS transistors.

机译：MOS晶体管的深亚微米漏极电流和电荷模型。

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摘要

A unified short-channel Metal-oxide-semiconductor (S-CMOS) transistor model has been developed for design and simulation of deep-submicron mixed-signal very large-scale integration (VLSI) circuits for high-speed computing, high-frequency communication, and multimedia applications. Unified expressions for drain current, conductances, terminal charge, and capacitances are derived with the assistance of three smooth functions including hyperbola, exponential interpolation, and sigmoid functions, which provide excellent transitions between different regions of operation. A compact set of 35 parameters is used to characterize transistor behavior. Effects of non-uniform substrate doping, drain-induced-barrier-lowering, narrow-channel and reverse short-channel are included in the threshold voltage expression. Mobility reduction due to lateral and vertical electrical fields is modeled by including the second-order term to provide high accuracy for deep-submicron transistors. The charge/capacitance model uses an accurate formulation for back-gate degradation coefficient to model the channel charge density. The unified expressions of charge densities are derived which are valid for all operation regions including the accumulation region. Different channel-charge partitioning schemes, including 40/60, 0/100, and 50/50, are provided to have better usage of the model in various applications. Parameter extraction of S-CMOS model is based on physical meaning of each model parameter, and is implemented by using MATLAB program. Both the local determination and global optimization strategies are combined to increase the extraction accuracy and reduce computation time. The S-CMOS model is implemented in a modified version of the popular SPICE-3f3 circuit simulator from University of California, Berkeley. Simulation results of mixed-signal circuits including domino logic gate, folded-cascode operational amplifier, analog comparator, wide-range Gilbert multiplier, and DRAM circuit are presented. Comparison of simulated results and measured data of transistors demonstrate the accuracy of the S-CMOS model and its strong capability in the deep-submicron technologies. In the appendix, research work on modeling MOS transistors for use up to 10 GHz is described with careful comparison of measured and simulation results.
机译：已经开发出统一的短通道金属氧化物半导体（S-CMOS）晶体管模型，用于设计和仿真用于高速计算，高频通信的深亚微米混合信号超大规模集成电路（VLSI）电路以及多媒体应用程序。借助三个平滑函数（包括双曲线，指数插值和S形函数）的帮助，导出了漏极电流，电导，端子电荷和电容的统一表达式，它们在不同的操作区域之间提供了出色的过渡。一组紧凑的35个参数用于表征晶体管的行为。在阈值电压表达式中包括不均匀的衬底掺杂，漏极引起的势垒降低，窄沟道和反向短沟道的影响。通过包括二阶项来模拟由于横向和垂直电场引起的迁移率降低，从而为深亚微米晶体管提供高精度。电荷/电容模型使用精确的公式表示背栅退化系数，以建模沟道电荷密度。推导电荷密度的统一表达式，该表达式对于包括累积区域在内的所有操作区域均有效。提供了不同的通道电荷划分方案，包括40 / 60、0 / 100和50/50，以在各种应用中更好地利用该模型。 S-CMOS模型的参数提取基于每个模型参数的物理含义，并使用MATLAB程序实现。结合了局部确定和全局优化策略，可以提高提取精度并减少计算时间。 S-CMOS模型在加利福尼亚大学伯克利分校流行的SPICE-3f3电路仿真器的修改版中实现。给出了包括多米诺逻辑门，折叠共源共栅运算放大器，模拟比较器，宽范围吉尔伯特乘法器和DRAM电路在内的混合信号电路的仿真结果。对晶体管的仿真结果和测量数据进行比较，证明了S-CMOS模型的准确性及其在深亚微米技术中的强大能力。在附录中，通过仔细比较测量结果和仿真结果，描述了在高达10 GHz的频率下使用MOS晶体管建模的研究工作。

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  • 作者

    Jen, Hung-Min.;

  • 作者单位

    University of Southern California.;

  • 授予单位 University of Southern California.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 1998
  • 页码 197 p.
  • 总页数 197
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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