• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文学位 >Basic issues in synchronous digital hierarchy networks.
【24h】

Basic issues in synchronous digital hierarchy networks.

机译：同步数字体系网络中的基本问题。

获取原文
获取原文并翻译 | 示例
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Frame synchronization, multiplexing and error detection are three basic issues in Synchronous Digital Hierarchy (SDH) transmission networks. The relative techniques are required for meeting efficient and correct digital signal transmission in high speed digital communication networks. According to a group of ITU-T recommendations G.707, G.708 and G.709, this dissertation deals with research on the basic issues of frame synchronization, multiplexing and estimation of errored block detection for STM-1 system with a rate of 155.520 Mbits/s in SDH networks. In this framework, first, we present an entirely novel parallel processing-based frame synchronization system and analyze its performance. By using a parallel approach, we are able to process in SDH system at a rate of 19.44 MHZ. This means that all functions, such as descramble, section overhead monitoring, pointer processing, etc., are operated at byte rate after the framer. All of these functions must be done on a byte wide basis. Thus all operations are performed in parallel in an SDH processor. The scheme is expected to relax operating speed requirements and simplify complexity of the circuits used in the system. The proposed methodology can be implemented using off-the-shelf low-rate integrated circuits (ICs) without sacrificing performance. In the second part of this dissertation, we present a method for multiplexing C-3 pay-load in the STM-1 structure. Our technique eliminates signal rate variations, which occur in various multiplexing structures in the SDH networks, by using a buffer. Calculations related to the buffer capacity for C-3 payload are also presented. In the third part of the dissertation, we study bit interleave parity (BIP) code performance, find a close form to solve the probability of undetected error, and give a group of curves for estimating errored block rate. This work is based on the features of BIP code.; Although our study is based on the STM-1 frame structure, the proposed methodologies are expected to be efficient solutions for implementing other STM-N systems.
机译：帧同步，多路复用和错误检测是同步数字体系（SDH）传输网络中的三个基本问题。为了满足高速数字通信网络中有效和正确的数字信号传输，需要相关技术。根据一组ITU-T建议G.707，G.708和G.709，本文针对STM-1系统的帧同步，复用和误块检测估计的基本问题进行了研究。 SDH网络中为155.520 Mbit / s。在此框架中，首先，我们提出了一种全新的基于并行处理的帧同步系统，并分析了其性能。通过使用并行方法，我们能够以19.44 MHZ的速率在SDH系统中进行处理。这意味着所有功能，例如解密，段开销监视，指针处理等，都在成帧器之后以字节速率进行操作。所有这些功能必须在字节宽的基础上完成。因此，所有操作都在SDH处理器中并行执行。该方案有望放宽对工作速度的要求，并简化系统中使用的电路的复杂性。可以使用现成的低速率集成电路（IC）来实现所提出的方法，而不会牺牲性能。在本文的第二部分，我们提出了一种在STM-1结构中复用C-3有效载荷的方法。我们的技术通过使用缓冲器消除了SDH网络中各种复用结构中出现的信号速率变化。还介绍了与C-3有效载荷的缓冲区容量有关的计算。在论文的第三部分，我们研究了比特交织奇偶校验（BIP）码的性能，找到了一种近似形式来解决未检测到的错误的可能性，并给出了一组估计错误块率的曲线。这项工作基于BIP代码的功能。尽管我们的研究基于STM-1框架结构，但预期所提出的方法是实现其他STM-N系统的有效解决方案。

著录项

  • 作者

    Teng, Jun.;

  • 作者单位

    City University of New York.;

  • 授予单位 City University of New York.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 1997
  • 页码 99 p.
  • 总页数 99
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号