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Une methode de multi-partitionnenment de circuits VLSI en vue d'un placement et routage.

机译：一种VLSI电路的多分区方法，用于布局和布线。

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摘要

The design of integrated circuits in micro-electronics requires layout mask drawings which are obtained with two tasks: placement and routing. This work contains a first study of various automatic placement techniques. We then study the chosen placement technique: partitioning. Given as input a VLSI circuit described as a set of interconnected cells, partitioning consists of dividing the cells of the circuit into n parts guided by a given objective function. The present research paper therefore deals with the development of a new multi-partitioning method adapted to VLSI circuits.;Attempting to minimize the total length of the interconnections while maintaining parts of proportional sizes, the choice of the cells to move from one part to another is guided by alternating objectives. The method either tries to optimize the balance between the sizes of the parts or aims at optimizing the cut (number of nets that link the parts). A flexible net cost function enables a good approximation of the interconnection lengths in order to estimate the quality of the partitioning.;The partitioning method developed generates experimental results of good quality. Both the memory space needed and the execution times vary linearly with the number of parts generated. The memory space required also varies linearly with the number of cell of the circuits. The execution times, on the other hand were not clearly related to the number of cells. These time results were more clearly related to the number of improvement loops needed before the heuristic encounters the stopping criterion. Moreover, the experimental results demonstrate that the disproportion constants (final disproportion wanted, tolerated disproportion, etc.) have a great influence on the quality of the partitioning. (Abstract shortened by UMI.)
机译：微电子集成电路的设计需要布局掩模图，这是通过两个任务获得的：布局和布线。这项工作包含对各种自动放置技术的首次研究。然后，我们研究所选的放置技术：分区。给定一个描述为一组互连单元的VLSI电路作为输入，划分包括将电路的单元划分为由给定目标函数引导的n个部分。因此，本研究论文致力于开发一种适用于VLSI电路的新的多分区方法。;试图在保持部分比例尺寸的同时最小化互连的总长度，选择从一个部分移动到另一个部分的单元以交替的目标为指导。该方法要么尝试优化零件尺寸之间的平衡，要么旨在优化切割（连接零件的网的数量）。灵活的净成本函数可以很好地近似互连长度，以便估计分区的质量。所开发的分区方法产生了高质量的实验结果。所需的存储空间和执行时间都随生成的零件数量线性变化。所需的存储空间也随电路单元数线性变化。另一方面，执行时间与单元数没有明显关系。这些时间结果与启发式方法遇到停止标准之前所需的改进循环数更为明显。此外，实验结果表明，歧化常数（所需的最终歧化，容许的歧化等）对分区的质量有很大的影响。 （摘要由UMI缩短。）

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  • 作者

    Guette, Joelle.;

  • 作者单位

    Ecole Polytechnique, Montreal (Canada).;

  • 授予单位 Ecole Polytechnique, Montreal (Canada).;
  • 学科 Engineering Electronics and Electrical.
  • 学位 M.Sc.A.
  • 年度 1996
  • 页码 166 p.
  • 总页数 166
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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