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首页> 外文学位 >FPGA design of a CDMA system for multiuser detection based on iterative processing.
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FPGA design of a CDMA system for multiuser detection based on iterative processing.

机译：基于迭代处理的用于多用户检测的CDMA系统的FPGA设计。

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摘要

This thesis details the development of an enhanced Coded Division Multiple Access (CDMA) Multiuser Detection (MUD) receiver in a Field Programmable Gate Array (FPGA) environment. The design is defined and generated in C++ and then confirmed through Hardware Design Language (HDL) behavioural simulation in ModelSim and through implementation in a Virtex II and Virtex IV FPGA development board. The Lyrtech development board utilizes C generated test vectors and is controlled through an interactive C terminal. The terminal allows extraction of test results, while simultaneously giving control of system parameters in the FPGA. The largest design explored has 50 users, which demonstrates a system toad of 1.5625. This design utilizes over 80% of the Virtex IV slice resources. The throughput for a single user is 3Mb/s with a large user system able to attain 192Mb/s burst throughput. The design is not optimized for throughput but instead minimized for logic size and FPGA utilization, so that a large number of users can be packed onto a single FPGA. Resource sharing techniques as well as logic simplification and pipeline reordering are used to minimize control overhead as well as utilization of FPGA slice logic. Design tradeoffs are explored within the system with respect to Bit Error Rate (BER) performance. Practical precisions within the receiver are revealed through C++ simulations. The receiver utilizes an iterative joint cancellation scheme to reduce the impact of multiaccess interference from other users. The cancellation is performed with soft information and is a simple interference cancellation method. It is also shown that the system has potential for analog Very Large Scale Integration (VLSI) implementation.
机译：本文详细介绍了在现场可编程门阵列（FPGA）环境中增强型CDMA多用户检测（MUD）接收机的开发。该设计是用C ++定义和生成的，然后通过ModelSim中的硬件设计语言（HDL）行为仿真以及在Virtex II和Virtex IV FPGA开发板上的实现进行确认。 Lyrtech开发板利用C生成的测试向量，并通过交互式C终端进行控制。该终端允许提取测试结果，同时控制FPGA中的系统参数。探索的最大设计有50个用户，展示了系统蟾蜍1.5625。该设计利用了80％以上的Virtex IV Slice资源。一个大型用户系统的单个用户的吞吐量为3Mb / s，能够实现192Mb / s的突发吞吐量。该设计并未针对吞吐量进行优化，而是针对逻辑大小和FPGA利用率进行了最小化，因此可以将大量用户打包到单个FPGA中。资源共享技术以及逻辑简化和流水线重排序用于最大程度地减少控制开销以及FPGA Slice逻辑的利用率。在系统内就误码率（BER）性能进行了设计折衷。接收器内的实际精度通过C ++仿真显示出来。接收器利用迭代联合抵消方案来减少来自其他用户的多址干扰的影响。消除是利用软信息执行的，并且是一种简单的干扰消除方法。还表明该系统具有实现模拟超大规模集成（VLSI）的潜力。

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  • 作者

    Dodd, Russell.;

  • 作者单位

    University of Alberta (Canada).;

  • 授予单位 University of Alberta (Canada).;
  • 学科 Engineering Electronics and Electrical.
  • 学位 M.Sc.
  • 年度 2009
  • 页码 73 p.
  • 总页数 73
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 老年病学;
  • 关键词

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