As the complexity of VLSI devices and systems continues to grow, designers must become increasingly sensitive to system performance and reliability issues. The application of system-level built-in self-test (BIST) will increase in importance, and with it the requirements for an integrated and reliable maintenance network support infrastructure. This dissertation describes the application of fault-tolerant network concepts and evaluation techniques to dedicated BIST maintenance networks (MNets).;Deficiencies with existing maintenance network approaches are shown to include the lack of self-testing capabilities, no ability to gracefully degrade, and catastrophic impact of single point failures. In response to these problems, a methodology is developed for the design and evaluation of dedicated MNets within a testing hierarchy. Based on this methodology, the components that contribute to network failures are categorized into failure classes, and their failure distributions are determined. At the wafer scale integration hierarchical level, which this dissertation evaluates, interconnection electromigration failures are identified as the primary failure mechanism and are approximated by a Weibull distribution. Three new fault-tolerant MNet architectures are proposed based on loop and bus topologies. Two of these architectures utilize distributed maintenance processors to reduce test time.;The reliability, or "success" of existing and proposed MNet architectures is determined, and shows that there is a substantial difference in useful lifetimes of these systems. Those which utilize more redundance offer increased reliability. Performability, or the "work" accomplished by the system, is a measure which combines performance and reliability analysis and is introduced and identified as an appropriate measure for evaluating MNet architectures. Several new performance structures are proposed in order to apply performability to MNets. A performability analysis utilizing these performance structures show that, unlike reliability, the useful "work" obtained from these architectures can be grouped into two categories: those which are highly redundant and utilize distributed maintenance processors, and those less redundant architectures which use a single maintenance processor.
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