• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文学位 >Automatic design and optimization of processor data path and memory hierarchy.
【24h】

Automatic design and optimization of processor data path and memory hierarchy.

机译：自动设计和优化处理器数据路径和内存层次结构。

获取原文
获取原文并翻译 | 示例
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

The stringent performance and power requirements of modem applications have fueled the need for application specific computing platforms. Conventional general purpose embedded processor do not provide the necessary throughput for meeting the applications' performance and power needs. On the other hand, manual hardware design is too expensive and results in inflexible implementation. The short time to market demands also make hardware design prohibitive. Therefore, there exists a need for automatic design methods and tools that provide a high performance, programmable and energy-efficient implementation starting from standard application descriptions such as C reference code. High level synthesis and application specific processor tools are a step in this direction, but suffer from scalability, quality and controllability issues. In this dissertation, we present techniques for automatic processor design from C code that are scalable to thousands of lines of C code, are controllable at each step of the design process and provide quality of results comparable to manual design.;Our contributions enable a system level design methodology for application specific processors that starts with a reference C code of the application. An initial processor data path is constructed from a database of available components such as function units, register files and buses. The initial data path is based on the types of operations and available concurrency in the application. The data path is then iteratively refined until an efficient architecture is derived. The key optimization goal is to keep performance within given boundaries while maximizing resource utilization. We further optimize the processor design using a novel algorithm for automatic custom pipelining based on the C code. The pipelining optimization also targets both resource utilization and performance. Our experimental results with large applications such as DCT and MP3 decoder show that automatically generated architectures are comparable to manual designs, but can be obtained in a matter of few seconds, leading to significant productivity gains.;Our final contribution to design methods for embedded systems deals with low power memory design. Typically, DRAM (dynamic random-access memory) energy consumption in low-power embedded systems can be very high, exceeding that of the data cache or even that of the processor. We present and evaluate a scheme for reducing the energy consumption of SDRAM (synchronous DRAM) memory access by a combination of techniques that take advantage of SDRAM energy efficiencies in bank and row access. This is achieved by using small, cache-like structures in the memory controller to prefetch an additional cache block(s) on SDRAM reads and to combine block writes to the same SDRAM row. The results quantify the SDRAM energy consumption of MiBench applications and demonstrate significant savings in SDRAM energy consumption, 23%, on average, and reduction in the energy-delay product, 44%, on average. The approach also improves performance: the CPI is reduced by 26%, on average.
机译：调制解调器应用对性能和功率的严格要求推动了对专用计算平台的需求。传统的通用嵌入式处理器无法提供满足应用程序性能和电源需求的必要吞吐量。另一方面，手动硬件设计过于昂贵，导致实施不灵活。上市时间短也使硬件设计望而却步。因此，需要一种自动设计方法和工具，其从诸如C参考代码之类的标准应用程序描述开始提供高性能，可编程和高能效的实现。高级综合和专用处理器工具是朝这个方向迈出的一步，但会遇到可伸缩性，质量和可控性问题。在本文中，我们提出了从C代码进行自动处理器设计的技术，这些技术可扩展到数千行C代码，并且在设计过程的每个步骤都是可控制的，并提供与手动设计相当的结果质量。以应用程序的参考C代码开头的专用处理器的高级设计方法。初始处理器数据路径由可用组件（例如功能单元，寄存器文件和总线）的数据库构成。初始数据路径基于操作的类型和应用程序中的可用并发。然后，反复优化数据路径，直到获得有效的体系结构。最关键的优化目标是将性能保持在给定范围内，同时最大程度地利用资源。我们使用基于C代码的自动自定义流水线的新颖算法，进一步优化了处理器设计。流水线优化还针对资源利用率和性能。我们在DCT和MP3解码器等大型应用程序上的实验结果表明，自动生成的体系结构可与手动设计相媲美，但可以在几秒钟内获得，从而大大提高了生产率。处理低功耗存储器设计。通常，低功耗嵌入式系统中的DRAM（动态随机存取存储器）能耗可能非常高，超过了数据高速缓存甚至是处理器的能耗。我们提出并评估了一种通过结合利用存储区和行访问中的SDRAM能源效率的技术来减少SDRAM（同步DRAM）存储器访问能耗的方案。这是通过在内存控制器中使用类似于缓存的小型结构来预取SDRAM读取中的一个或多个附加缓存块，并将块写入组合到同一SDRAM行中来实现的。结果量化了MiBench应用程序的SDRAM能耗，并证明了SDRAM能耗的显着节省（平均节省23％）和能耗产品的减少平均节省了44％。该方法还提高了性能：平均将CPI降低了26％。

著录项

  • 作者

    Trajkovic, Jelena.;

  • 作者单位

    University of California, Irvine.;

  • 授予单位 University of California, Irvine.;
  • 学科 Computer Science.
  • 学位 Ph.D.
  • 年度 2009
  • 页码 162 p.
  • 总页数 162
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 自动化技术、计算机技术;
  • 关键词

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号