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Dealing with test issues in typical ASIC design flow.

机译：在典型的ASIC设计流程中处理测试问题。

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摘要

As mainstream manufacturing process migrates to 40nm and beyond, designs are becoming more sensitive to the various variation sources. Due to the drive of low power application, supply voltage has been scaled aggressively. It does not only make the design more sensitive to change of voltage, but also makes traditionally secondary factors, such as temperature, impact the design performance more severely. As devices are placed more densely on the die, the design uncertainty is increasing due to various effects, such process variation, cross-talk, etc. The presence of design uncertainty makes the performance on silicon to be more statistically distributed. Thus, the test uncertainty increases, and maintaining the test quality is more difficult than ever. A more advanced test methodology is required to address the test uncertainty. This dissertation first discusses the design challenges that ASIC is facing, and then presents a study in silicon speed binning, which ASIC is adapting. Next we propose a framework to screening out defective samples and quantify amount of failure risk in passing samples with and without known good and bad samples. The framework can also guide test optimization based on statistical characteristic observed in test data.
机译：随着主流制造工艺向40nm及以上迁移，设计对各种变化源变得越来越敏感。由于驱动了低功率应用，因此电源电压已大幅度提高。它不仅使设计对电压的变化更加敏感，而且还使传统上次要的因素（例如温度）对设计性能的影响更为严重。随着器件在芯片上的密度更高，由于各种影响（例如工艺变化，串扰等），设计不确定性正在增加。设计不确定性的存在使硅片上的性能更加统计分布。因此，测试不确定性增加，并且保持测试质量比以往更加困难。需要一种更高级的测试方法来解决测试的不确定性。本文首先讨论了ASIC面临的设计挑战，然后提出了针对ASIC所适应的硅速度合并的研究。接下来，我们提出一个框架，以筛选出有缺陷的样本，并量化在有或没有已知好坏样本的情况下通过样本的失败风险量。该框架还可以根据在测试数据中观察到的统计特征来指导测试优化。

著录项

  • 作者

    Wu, Sean Hsi Yuan.;

  • 作者单位

    University of California, Santa Barbara.;

  • 授予单位 University of California, Santa Barbara.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2009
  • 页码 135 p.
  • 总页数 135
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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