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Rapid early design space exploration using legacy design data, technology scaling trend and in-situ macro models.

机译：利用遗留设计数据，技术缩放趋势和原位宏模型，可以快速进行早期设计空间探索。

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摘要

This work proposes a system level design framework for early design space exploration with a focus on power and performance tradeoffs using analytical power and performance prediction models. The analytical prediction models are driven by legacy design data, technology scaling trend, low level physical design parameters and in-situ simulations. Experiments on ISCAS benchmark circuits validate the feasibility of the proposed approach and yielded power centric designs that improved power by 7%--32% for a corresponding 0%--9% performance impact; or performance centric designs with improved performance of 11.25%--17% for a corresponding 2%--3.85% power penalty. Evolutionary algorithm based Pareto analysis on an industrial 65 nm design uncovered design tradeoffs which are not obvious to designers and optimize both power and performance. The high performance design option of the industrial design improved the straight-ported design's performance by 29% with a 2.5% power penalty, whereas the low power design option reduced the straight-ported design's power consumption by 40% for a 9% performance penalty.;The design framework and methodology developed and demonstrated in this work form the foundational steps for early design space exploration utilizing technology scaling trends, process dependent parameters and in-situ simulations. Analytical prediction models are currently limited only to predicting power and performance. Prediction models for yield, chip area and system reliability are seen as valuable future additions to EIDAs capability. Modeling the impact of process variation and the ability to incorporate statistical inputs and outputs are seen as an another incremental improvement to EIDAs value as a design tool. In addition to the above improvements, a macromodel based critical path delay calculation technique including clock and signal uncertainties, incorporating special libraries, RF and analog modules in the system model and, improving the evolutionary algorithm used for design space exploration are salient direction for future research. (Abstract shortened by UMI.)
机译：这项工作提出了用于早期设计空间探索的系统级设计框架，重点是使用分析能力和性能预测模型进行功率和性能折衷。分析预测模型由遗留设计数据，技术扩展趋势，底层物理设计参数和原位仿真驱动。在ISCAS基准电路上进行的实验验证了该方法的可行性，并产生了以功率为中心的设计，该设计将功率提高了7％-32％，从而对性能产生了0％-9％的影响;或以性能为中心的设计，其性能提高了11.25％-17％，相应的功率损失为2％-3.85％。在工业65 nm设计上基于演化算法的Pareto分析发现了设计折衷，这对设计人员而言并不明显，并且可以优化功耗和性能。工业设计的高性能设计选项将直端口设计的性能提高了29％，而功耗却降低了2.5％，而低功耗设计选项将直端口设计的功耗降低了40％，而性能却降低了9％。 ；在这项工作中开发和演示的设计框架和方法论构成了利用技术规模趋势，与工艺有关的参数和原位模拟来进行早期设计空间探索的基本步骤。目前，分析预测模型仅限于预测功率和性能。成品率，芯片面积和系统可靠性的预测模型被视为EIDA功能的宝贵未来补充。对过程变化的影响进行建模以及将统计输入和输出进行合并的能力被视为对EIDA值作为设计工具的又一次增量改进。除了上述改进之外，基于宏模型的关键路径延迟计算技术（包括时钟和信号不确定性），在系统模型中包含特殊库，RF和模拟模块以及改进用于设计空间探索的进化算法，是未来研究的重要方向。 。 （摘要由UMI缩短。）

著录项

  • 作者

    Thangaraj, Charles V.K.;

  • 作者单位

    Colorado State University.;

  • 授予单位 Colorado State University.;
  • 学科 Engineering Computer.
  • 学位 Ph.D.
  • 年度 2009
  • 页码 192 p.
  • 总页数 192
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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