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Design Space Exploration of Parallel Algorithms and Architectures for Wireless Communication and Mobile Computing Systems

机译：无线通信和移动计算系统并行算法和架构的设计空间探索

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摘要

During past several years, there has been a trend that the modern mobile SoC (system-on-chip) chipsets start to incorporate in one single chip the functionality of several general purpose processors and application-specific accelerators to reduce the cost, the power consumption and the communication overhead. Given the ever-growing performance requirements and strict power constraints, the existence of different types of signal processing workloads have posed challenges to the mapping of the computationally-intensive algorithms to the heterogeneous architecture of the mobile SoCs. Many such signal processing workloads such as channel decoding for wireless communication modem and mobile computer vision applications have high computational complexity, which requires accelerators implemented with parallel algorithms and architectures to meet the performance requirements. Partitioning the workloads and deploying them with the appropriate components of mobile chipsets are crucial to fully utilize the mobile SoC's heterogeneous architecture.;The goal of this thesis is to study parallel algorithms and architecture of high performance signal processing accelerators for several representative application workloads in wireless communication and mobile computing systems. We explore the design space of the parallel algorithms and architectures and highlight the workload partitioning and architecture-aware optimization schemes including algorithmic optimization, data structure optimization, and memory access optimization to improve the throughput performance and hardware (or energy) efficiency. As case studies, we will first propose contention-free interleaver architecture for parallel turbo decoding, which enables high throughput multi-standard turbo decoding ASIC (application-specific integrated circuit) with efficient hardware. Secondly, we propose massively parallel LDPC (low-density parity-check) decoding algorithm and implementation using GPU (graphics processor unit), which leads to high throughput and low latency LDPC decoding for practical SDR (software-defined radio) systems. Furthermore, we take advantage of the heterogeneous mobile CPU and GPU to accelerate representative mobile computer vision algorithms such as image editing and local feature extraction algorithms. Based on algorithm analysis and experimental results from the above case studies, we finally explore the design space and compare the performance of accelerator architectures for wireless communication and mobile vision use cases. We will show that the heterogeneous architecture of mobile systems is the key to efficiently accelerating parallel algorithms in order to meet the growing requirements of performance, efficiency, and flexibility.
机译：在过去的几年中，趋势是现代移动SoC（片上系统）芯片组开始将多个通用处理器和专用加速器的功能整合到一个芯片中，以降低成本和功耗和通讯开销。鉴于不断增长的性能要求和严格的功率限制，不同类型的信号处理工作负载的存在给将计算密集型算法映射到移动SoC的异构体系结构提出了挑战。许多此类信号处理工作负载（例如，用于无线通信调制解调器的信道解码和移动计算机视觉应用程序）具有很高的计算复杂度，这需要使用并行算法和体系结构实现的加速器来满足性能要求。对工作负载进行分区并将其与移动芯片组的适当组件一起部署对于充分利用移动SoC的异构体系结构至关重要。;本论文的目的是研究用于无线中若干代表性应用工作负载的高性能信号处理加速器的并行算法和体系结构通信和移动计算系统。我们探索了并行算法和体系结构的设计空间，并重点介绍了工作负载划分和可感知体系结构的优化方案，包括算法优化，数据结构优化和内存访问优化，以提高吞吐量性能和硬件（或能源）效率。作为案例研究，我们将首先提出用于并行Turbo解码的无竞争交织器架构，该架构可通过高效的硬件实现高吞吐量的多标准Turbo解码ASIC（专用集成电路）。其次，我们提出了大规模并行的LDPC（低密度奇偶校验）解码算法和使用GPU（图形处理器单元）的实现，这为实际的SDR（软件定义的无线电）系统带来了高吞吐量和低延迟的LDPC解码。此外，我们利用异构移动CPU和GPU来加速代表性的移动计算机视觉算法，例如图像编辑和局部特征提取算法。基于上述案例研究的算法分析和实验结果，我们最终探索了设计空间，并比较了用于无线通信和移动视觉用例的加速器体系结构的性能。我们将展示移动系统的异构体系结构是有效加速并行算法以满足性能，效率和灵活性不断增长的要求的关键。

著录项

  • 作者

    Wang, Guohui.;

  • 作者单位

    Rice University.;

  • 授予单位 Rice University.;
  • 学科 Electrical engineering.
  • 学位 Ph.D.
  • 年度 2014
  • 页码 259 p.
  • 总页数 259
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

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