This thesis studies the possibility of building efficient all-silicon pulse-compression nonlinear transmission lines (NLTLs). The theory and history of NLTLs are thoroughly reviewed, and the motivation for this project and possible applications are discussed. Silicon coplanar waveguide (CPW) lines and CMOS varactors, as two key components in NLTLs, are fully researched, and were fabricated using a standard 0.18-mum CMOS process. To reduce the dielectric loss caused by the conductive silicon substrate, a slow-wave transmission line technique was further developed, and silicon slow-wave CPW lines were built. A measured S21 loss of only 0.25 dB/mm at 40 GHz is achieved, with an effective relative permittivity as high as 25. Six different types of varactors based on NMOS transistors were investigated. They were divided into two groups: one has monotonic capacitance-voltage curves, and the other has non-monotonic curves. This study demonstrates that the first group is more suited for single-edge, the other for double-edge pulse-sharpening. The NMOS varactors used in the final NLTL designs were fabricated and on-chip measurements up to 55-GHz were made. NLTL transient simulations based on component measurements show a leading-edge rise time reduction of 75% for single-edge, and 60% for double-edge pulse sharpening. Following the investigation of the components, two types of NLTL circuits were designed and built on two CMOS 0.18-mum chips, one was designed for single-edge, the other for double-edge pulse compression. Large-signal measurements, based on the newly developed X-parameter method, show a significant compression with the second type of NLTL However, because of its large attenuation, only minor compression is obtained with the first type of NLTL. This research successfully demonstrates that it is possible to build pulse-compression NLTLs on low-cost commercial CMOS chips.
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机译：本文研究了构建高效的全硅脉冲压缩非线性传输线（NLTL）的可能性。对NLTL的理论和历史进行了全面回顾，并讨论了该项目的动机和可能的应用。硅共面波导（CPW）线和CMOS变容二极管作为NLTL中的两个关键组件，已经得到了充分的研究，并使用标准的0.18微米CMOS工艺制造。为了减少由导电硅衬底引起的介电损耗，进一步发展了慢波传输线技术，并建立了硅慢波CPW线。在40 GHz下测得的S21损耗仅为0.25 dB / mm，有效相对介电常数高达25。研究了基于NMOS晶体管的六种不同类型的变容二极管。它们分为两组：一组具有单调电容-电压曲线，另一组具有非单调曲线。这项研究表明，第一组更适合单边脉冲，另一组更适合双边脉冲锐化。制造了最终NLTL设计中使用的NMOS变容二极管，并进行了高达55 GHz的片上测量。基于组件测量的NLTL瞬态仿真表明，单边脉冲前沿上升时间减少了75％，双脉冲锐化则减少了60％。在研究了组件之后，设计了两种类型的NLTL电路，并建立在两块CMOS 0.18微米CMOS芯片上，一种用于单边，另一种用于双边脉冲压缩。基于新开发的X参数方法的大信号测量结果显示，第二种NLTL具有显着的压缩效果。但是，由于其衰减较大，因此第一种NLTL仅可获得较小的压缩率。这项研究成功地证明，可以在低成本的商用CMOS芯片上构建脉冲压缩NLTL。
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