• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文学位 >Inter-Module Interfacing Techniques for SoCs with Multiple Clock Domains to Address Challenges in Modern Deep Sub-Micron Technologies.
【24h】

Inter-Module Interfacing Techniques for SoCs with Multiple Clock Domains to Address Challenges in Modern Deep Sub-Micron Technologies.

机译：具有多个时钟域的SoC的模块间接口技术，可应对现代深亚微米技术中的挑战。

获取原文
获取原文并翻译 | 示例
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

Miniaturization of integrated circuits (ICs) due to the improvement in lithographic techniques in modern deep sub-micron (DSM) technologies allows several complex processing elements to coexist in one IC, which are called System-on-Chip. As a first contribution, this thesis quantitatively analyzes the severity of timing constraints associated with Clock Distribution Network (CDN) in modern DSM technologies and shows that different processing elements may work in different dock domains to alleviate these constraints. Such systems are known as Globally Asynchronous Locally Synchronous (GALS) systems.;This thesis also addresses the dock skew challenges faced by high-performance synchronous interfacing methodologies in modern DSM technologies. The proposed methodology allows communicating modules to run at a frequency that is independent of the dock skew. Leveraging a novel clock-scheduling algorithm, our technique permits a faster module to communicate safely with a slower module without slowing down. Safe data communications for mesochronous schemes and for the cases when communicating modules have dock frequency ratios of integer or coprime numbers are theoretically explained and experimentally demonstrated. A clock-scheduling technique to dynamically accommodate phase variations is also proposed. These methods are implemented to the Xilinx Virtex II Pro technology. Experiments prove that the proposed interfacing scheme allows modules to communicate data safely, for mesochronous schemes, at 350 MHz, which is the limit of the technology used, under a dock skew of more than twice the time period (i.e. a dock skew of 12 ns).;It is imperative that different processing elements of a GALS system need to communicate with each other through some interfacing technique, and these interfaces can be asynchronous or synchronous. Conventionally, the asynchronous interfaces are described at the Register Transfer Logic (RTL) or system level. Such designs are susceptible to certain design constraints that cannot be addressed at higher abstraction levels; crosstalk glitch is one such constraint. This thesis initially identifies, using an analytical model, the possibility of asynchronous interface malfunction due to crosstalk glitch propagation. Next, we characterize crosstalk glitch propagation under normal operating conditions for two different classes of asynchronous protocols, namely bundled data protocol based and delay insensitive asynchronous designs. Subsequently, we propose a logic abstraction level modeling technique, which provides a framework to the designer to verify the asynchronous protocols against crosstalk glitches. The utility of this modeling technique is demonstrated experimentally on a Xilinx Virtex-II Pro FPGA. Furthermore, a novel methodology is proposed to quench such crosstalk glitch propagation through gating the asynchronous interface from sending the signal during potential glitch vulnerable instances. This methodology is termed as crosstalk glitch gating. This technique is successfully applied to obtain crosstalk glitch quenching in the representative interfaces.
机译：由于现代深亚微米（DSM）技术中的光刻技术的改进，集成电路（IC）的小型化使多个复杂的处理元件可以共存于一个IC中，这被称为片上系统。作为第一贡献，本文定量分析了现代DSM技术中与时钟分配网络（CDN）相关的时序约束的严重性，并表明不同的处理元素可以在不同的对接域中工作以减轻这些约束。这种系统被称为全局异步本地同步（GALS）系统。本文还解决了现代DSM技术中高性能同步接口方法所面临的扩展坞倾斜问题。所提出的方法允许通信模块以与坞站偏斜无关的频率运行。利用一种新颖的时钟调度算法，我们的技术允许较快的模块与较慢的模块安全通信，而不会降低速度。从理论上解释并通过实验证明了用于同步方案以及通讯模块具有整数或互质数的坞站频率比的情况的安全数据通信。还提出了一种时钟调度技术来动态适应相位变化。这些方法已在Xilinx Virtex II Pro技术中实现。实验证明，对于同步方案，所提出的接口方案允许模块在350 MHz频率（这是所使用技术的限制）下，在超过两倍时间周期的扩展坞倾斜（即12 ns的扩展坞倾斜）下安全地通信数据）。至关重要的是，GALS系统的不同处理元素需要通过某种接口技术相互通信，并且这些接口可以是异步的或同步的。按照惯例，异步接口是在寄存器传输逻辑（RTL）或系统级别上描述的。这样的设计容易受到某些设计约束的影响，而这些约束在更高的抽象级别上无法解决。串扰故障就是这种限制之一。本文首先使用分析模型确定了由于串扰毛刺传播而引起的异步接口故障的可能性。接下来，我们针对两种不同类型的异步协议，即基于捆绑数据协议的和对延迟不敏感的异步设计，在正常工作条件下表征串扰毛刺传播。随后，我们提出了一种逻辑抽象级建模技术，该技术为设计人员提供了一个框架，以验证针对串扰故障的异步协议。在Xilinx Virtex-II Pro FPGA上通过实验证明了该建模技术的实用性。此外，提出了一种新颖的方法，可通过控制异步接口以防止潜在的故障易损实例发送信号来抑制此类串扰故障传播。这种方法称为串扰毛刺选通。该技术已成功应用于代表界面中的串扰毛刺猝灭。

著录项

  • 作者

    Hasan, Syed Rafay.;

  • 作者单位

    Concordia University (Canada).;

  • 授予单位 Concordia University (Canada).;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2009
  • 页码 239 p.
  • 总页数 239
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类
  • 关键词

  • 入库时间 2022-08-17 11:38:13

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号