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NMOS low drop out voltage regulator with switched floating capacitor gate overdrive.

机译:NMOS低压差稳压器,带有开关式浮动电容器栅极过驱动。

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摘要

This thesis presents a fully integrated low dropout voltage (LDO) regulator using an NMOS transistor as the output pass element. It uses a novel switched capacitor scheme that raises the control voltage above the supply voltage level, thus increasing the voltage headroom and allowing the low dropout operation of the voltage regulator. The described method allows continuous time operation of the LDO regulator.;Several different circuit topologies to implement this approach are presented; each one of them is properly analyzed and explained. A comparison between the different present topologies as well as with previous reported work is presented.;The regulator is designed using a regular 0.13 mum CMOS process. It is capable of delivering a 1.5 V at a loading of 50 mA with a dropout voltage of 0.1 V, and is stable for a wide load current range with loading capacitances up to 100 pF. The output variation when a full load step is applied is 60 mV and the recovery time is 0.2 mus. The total on-chip capacitance is less than 7 pF which results in an area of less than 0.009 mm2. Additionally, the power consumption is low with a quiescent current of 120 muA. Extensive simulation results demonstrate the feasibility of the proposed design.
机译:本文提出了一种使用NMOS晶体管作为输出通过元件的完全集成的低压降(LDO)稳压器。它使用一种新颖的开关电容器方案,该方案将控制电压提高到电源电压电平以上,从而增加了电压裕量并允许调压器的低压差工作。所描述的方法允许LDO稳压器连续时间运行。提出了几种不同的电路拓扑来实现该方法;他们每个人都经过适当的分析和解释。给出了当前不同拓扑之间的比较以及与先前报道的工作之间的比较。稳压器采用常规的0.13um CMOS工艺设计。它能够在50 mA负载下以1.5 V的压降提供1.5 V的电压,并且在负载电容高达100 pF的宽负载电流范围内稳定。施加满负载阶跃时的输出变化为60 mV,恢复时间为0.2 mus。总的片上电容小于7 pF,这导致面积小于0.009平方毫米。此外,静态电流为120μA时功耗很低。大量的仿真结果证明了所提出设计的可行性。

著录项

  • 作者单位

    Southern Methodist University.;

  • 授予单位 Southern Methodist University.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 M.S.
  • 年度 2009
  • 页码 71 p.
  • 总页数 71
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

  • 入库时间 2022-08-17 11:38:27

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