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Efficient algorithm and architecture for implementation of multiplier circuits in modern FPGAs.

机译：在现代FPGA中实现乘法器电路的高效算法和架构。

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High speed multiplication in Field Programmable Gate Arrays is often performed either using logic cells or with built-in DSP blocks. The latter provides the highest performance for arithmetic operations while being also optimized in terms of power and area utilization. Scalability of input operands is limited to that of a single DSP block and the current CAD tools provide little help when the designer needs to build larger arithmetic blocks. The present thesis proposes an effective approach to the problem of building large integer multipliers out of smaller ones by giving two algorithms to the system designer, for a given FPGA technology. Large word length is required in applications such as cryptography and video processing. The first proposed algorithm partitions large input multipliers into an architecture-aware design. The second algorithm then places the generated design in an optimal layout minimizing interconnect delay. The thesis concludes with simulation and hardware generated data to support the proposed algorithms.

机译：现场可编程门阵列中的高速乘法通常使用逻辑单元或内置DSP模块来执行。后者为算术运算提供了最高的性能，同时在功耗和面积利用率方面也得到了优化。输入操作数的可扩展性仅限于单个DSP模块的可扩展性，当设计人员需要构建较大的算术模块时，当前的CAD工具提供的帮助很少。本文针对给定的FPGA技术，通过向系统设计人员提供两种算法，提出了一种从较小的整数乘法器构建大型整数乘法器的有效方法。在诸如密码学和视频处理之类的应用中，要求大字长。第一个提出的算法将大型输入乘法器划分为具有体系结构的设计。然后，第二种算法将生成的设计置于最佳布局中，以最大程度地减少互连延迟。本文以仿真和硬件生成的数据作为结论来支持所提出的算法。

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作者
Athow, Jacques Laurent.;
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作者单位

Concordia University (Canada).;

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授予单位 Concordia University (Canada).;
学科 Engineering Computer.
学位 M.A.Sc.
年度 2008
页码 115 p.
总页数 115
原文格式 PDF
正文语种 eng
中图分类
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专利

1. Implementation of Efficient FFT Algorithms on Fused Multiply- Add Architectures [J] . Linzer E.N., Feig E. IEEE Transactions on Signal Processing . 1993,第期

机译：在融合乘法加法架构上实现高效FFT算法
2. A Power Efficient Binary Multiplier Circuit with Overflow Detection Using Single Spin Logic Circuit: Design and Implementation [J] . Ankush Ghosh, Souvik Sarkar, D. Ray Chaudhuri, Advanced Science Letters . 2009,第3期

机译：使用单自旋逻辑电路的具有溢出检测功能的高效率二进制乘法器电路：设计和实现
3. Application Specific Integrated Circuit Implementation of Multiplier Free Modified Flipping Architecture for Image Compression [J] . Parvatham Vijay, Seetharaman Gopalakrishnan Advanced Science Letters . 2014,第10a12期

机译：用于图像压缩的无乘数修正翻转架构的专用集成电路实现
4. Efficient FPGA Implementation Architecture of Fast FIR Algorithm Using Han-Carlson Adder Based Vedic Multiplier [C] . Payal Paliwal, Janki Ballabh Sharma International Conference on Inventive Research in Computing Applications . 2018

机译：基于Han-Carlson加法器的吠陀乘法器的快速FIR算法的高效FPGA实现架构
5. Modeling, circuits and architectures for power -efficient FPGAs. [D] . Li, Fei. 2005

机译：高效FPGA的建模，电路和架构。
6. A novel reversible logic gate and its systematic approach to implement cost-efficient arithmetic logic circuits using QCA [O] . Peer Zahoor Ahmad, S.M.K. Quadri, Firdous Ahmad, 2017

机译：一种使用QCA实现具有成本效益的算术逻辑电路的新型可逆逻辑门及其系统方法
7. Efficient algorithm and architecture for implementation of multiplier circuits in modern EPGAs [O] . Athow Jacques Laurent 2008

机译：在现代EPGA中实现乘法器电路的高效算法和架构

Efficient algorithm and architecture for implementation of multiplier circuits in modern FPGAs.

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