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Analysis and design of on-chip phase noise measurement modules.

机译：片上相位噪声测量模块的分析和设计。

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摘要

An on-chip phase noise measurement module is presented. Unlike previously published monolithic measurement techniques that measure jitter in the time domain, the proposed circuit measures phase noise spectrum. The phase noise measurement module is fully integrated and does not require a spectrally clean reference clock or external calibration. The module can be integrated as part of a Built-In Self Test (BIST) scheme to characterize the close-in noise performance of Phase Locked Loops (PLLs) and Clock-Data Recovery (CDR) circuits. The proposed circuit uses a low-noise Voltage Controlled Delay-Line (VCDL) and mixer-based frequency discriminator to extract the phase noise fluctuations at baseband. The VCDL is used to convert the signal's frequency fluctuations into phase fluctuations; which are then converted by a mixer into voltage fluctuations. The signal is then processed through a combined Baseband LNA (BBLNA) and Low-Pass Filter (LPF) stage and either sent directly off-chip in analog form or sampled and digitized using an Analog-to-Digital Converter (ADC). A self-calibration circuit is used to operate the measurement circuit at its highest sensitivity point eliminating the impact of Process, Voltage and Temperature (PVT) variations on the measurement accuracy. The proposed circuit is fabricated using a 0.25 um digital CMOS process and operates up to a 2 GHz carrier frequency. Experimental results show that the measurement module has a Single Tone (ST) measurement sensitivity of -75 dBc and an equivalent phase noise sensitivity of -124 dBc/Hz at 100 kHz offset frequency.
机译：提出了片上相位噪声测量模块。与先前发布的在时域内测量抖动的单片测量技术不同，该电路可测量相位噪声频谱。相位噪声测量模块是完全集成的，不需要频谱干净的参考时钟或外部校准。该模块可以集成为内置自测（BIST）方案的一部分，以表征锁相环（PLL）和时钟数据恢复（CDR）电路的近距离噪声性能。所提出的电路使用低噪声压控延迟线（VCDL）和基于混频器的鉴频器来提取基带处的相位噪声波动。 VCDL用于将信号的频率波动转换为相位波动；然后由混频器将其转换为电压波动。然后，信号通过组合的基带LNA（BBLNA）和低通滤波器（LPF）级进行处理，并以模拟形式直接在片外发送，或者使用模数转换器（ADC）进行采样和数字化。自校准电路用于使测量电路在其最高灵敏度点工作，从而消除了过程，电压和温度（PVT）变化对测量精度的影响。所提出的电路是使用0.25 um数字CMOS工艺制造的，并在高达2 GHz的载波频率下工作。实验结果表明，该测量模块在100 kHz偏移频率下的单音（ST）测量灵敏度为-75 dBc，等效相位噪声灵敏度为-124 dBc / Hz。

著录项

  • 作者

    Khalil, Waleed.;

  • 作者单位

    Arizona State University.;

  • 授予单位 Arizona State University.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 2008
  • 页码 78 p.
  • 总页数 78
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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