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Bilinear algorithms and ASIC architectures for fast signal processing.

机译：用于快速信号处理的双线性算法和ASIC架构。

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This dissertation presents a formal hardware design approach using bilinear algorithms for fast digital signal processing (DSP) applications. In particular, we focus on the design of application specific integrated circuit (ASIC), where dedicated algorithmic accelerators are implemented in fixed-point arithmetic.;Most signal processing algorithms involve a transform kernel with a known structure. Using concepts of group theory, the kernel matrix can be recursively partitioned into computations of small length of cyclic convolutions and Hankel matrix products. Bilinear algorithms for these smaller blocks are then combined together to obtain the required bilinear algorithm of the transform. Bilinear algorithms have a high degree of concurrency as all multiplication operations are independent of each other and can be computed at the same time. As a result, the hardware realizations of bilinear algorithms are much faster than any other implementations. The structural modularity also allows simple pipelining and greatly reduces the number of input and output (IO) pins.;In this dissertation, we develop new bilinear algorithms and implementations for the discrete Hartley transform (DHT), the modified discrete cosine transform (MDCT) and the modulated complex lapped transform (MCLT). In case of bilinear DHT algorithms, we show that the kernel divisions are identical for all prime power lengths. Our implementations are 20%-60% faster than existing implementations. For MPEG-1/2 audio layer III (MP3) application, our proposed MDCT algorithms have about 30% lower computational complexity as compared with other fast algorithms in the literature. The modularity of our algorithms also permits one to design, for the first time, a unified architecture for forward and inverse transforms using different MP3 block sizes. In case of the MCLT, we achieve a bilinear algorithm by merging the external sine window function with the main computation through trigonometric manipulations. As compared with most algorithms, our MCLT algorithm requires about N -less multiplications, where the typical block size, N, for applications such as audio watermarking is 2048.
机译：本文提出了一种使用双线性算法进行快速数字信号处理（DSP）应用的形式化硬件设计方法。特别是，我们专注于专用集成电路（ASIC）的设计，其中专用算法加速器以定点算术实现。大多数信号处理算法都包含结构已知的变换内核。利用群论的概念，可以将核矩阵递归地划分为小长度的循环卷积和汉克尔矩阵积的计算。然后将这些较小块的双线性算法组合在一起，以获得所需的变换双线性算法。双线性算法具有很高的并发度，因为所有乘法运算都是彼此独立的，并且可以同时计算。结果，双线性算法的硬件实现比任何其他实现都快得多。结构模块化还允许简单的流水线化，并大大减少了输入和输出（IO）引脚的数量。本文为离散哈特利变换（DHT），改进的离散余弦变换（MDCT）开发了新的双线性算法和实现。以及调制的复杂重叠变换（MCLT）。在双线性DHT算法的情况下，我们表明对于所有素数功率长度，内核划分都是相同的。我们的实现比现有实现快20％-60％。对于MPEG-1 / 2音频层III（MP3）应用，与文献中的其他快速算法相比，我们提出的MDCT算法的计算复杂度降低了约30％。我们算法的模块性还允许人们首次设计使用不同MP3块大小的正向和反向转换的统一体系结构。在MCLT的情况下，我们通过将外部正弦窗函数与通过三角运算的主要计算进行合并来实现双线性算法。与大多数算法相比，我们的MCLT算法需要进行大约N倍的乘法运算，其中音频水印等应用的典型块大小N为2048。

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