集成电路工艺水平的提升，使得由单粒子瞬态脉冲造成的芯片失效越发不容忽视．为了准确计算单粒子瞬态脉冲对锁存器造成的失效率，提出一种考虑多时钟周期瞬态脉冲叠加的锁存窗屏蔽模型．使用提出的考虑扇出重汇聚的敏化路径逼近搜索算法查找门节点到达锁存器的敏化路径，并记录路径延迟；在扇出重汇聚路径上，使用提出的脉冲叠加计算方法对脉冲进行叠加；对传播到达锁存器的脉冲使用提出的锁存窗屏蔽模型进行失效率的计算．文中的锁存窗屏蔽模型可以准确计算扇出重汇聚导致的脉冲叠加，并对多时钟周期情形具有很好的适用性．针对ISCAS’85基准电路的软错误率评估结果表明，与不考虑多时钟周期瞬态脉冲叠加的方法相比，文中方法使用不到2倍的时间开销，平均提高7．5％的软错误率评估准确度．%Technology scaling results in that chip failure caused by single event transient pulses is becoming more and more serious.In order to accurately compute the failure rates introduced by the transient pulses impacting on latches,a novel latching-window masking model considering overlapped transient pulses in multi-cycle is proposed.Firstly,sensitized paths and delays are calculated by the proposed re-convergence aware sensitized path searching algorithm.Further,on re-conver-gence paths,pulses are overlapped by the proposed pulse overlapping calculation technique.Finally,as regards transient pul-ses arriving at latches,failure rates are computed by the proposed latching-window masking model.The proposed technique can accurately compute re-convergence induced pulse overlap and it is suitable to estimate failure rates considering multi-cy-cle.Experimental results for ISCAS'85 benchmarks show that,compared with the approach which has not considered pulse o-verlap in multi-cycle,the proposed technique improves 7.5% soft error rate accuracy on average with only less than twice the simulation time overhead.
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