The huge VLIW code size has brought serious problems to the capacity and energy consumption of instruction memory in stream architecture. Through analyzing the characteristics of instruction, this paper proposes a novel domain-divided VLIW compression scheme, designs a distributed on-chip instruction memory for stream architecture and proposes a new SIMD pipeline execution model. The experiment results show that about 38% of the off-chip instruction accessing and 65% of the on-chip instruction memory space demand can be reduced by the compression; the distributed instruction memory depresses about 37% of the area of on-chip instruction memory, and about 8.92 % of the area of MASA stream processor. At the same time, the energy consumption of the instruction memory is reduced by 61 % .%针对流体系结构中VLIW代码体积对指令存储器的容量和功耗带来的问题,本文通过分析流处理器的指令特征,提出了一种新的VLIW分域压缩技术.在此基础上,本文为流体系结构设计了分布式的片上指令存储器,并提出了SIMD流水的执行模式.实验结果证明,该技术减少了38％的片外指令访存,降低约65％的片上指令存储器空间需求;分布式指令存储器减少了约37％的片上指令存储器面积,使得MASA的系统面积降低了8.92％,并降低了61％的指令存储器功耗.
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