H.264 High Profile proposes the new 8 x 8 integer transform which achieves average bit-rate reduction of around 10％ for HD material. This paper presents an efficient architecture for H.264 multiple block-size inverse transform.2-D transform decomposition and common matrix operation extraction were applied to design general processing elements to simplify the implementation of transforms. The proposed architecture is both area-efficient (4807gates) and high performance (can provide real-time decoding of 4096 x 2048@60fps High Profile in 150MHz, 1.2G pixels/s data throughput rate, using TSMC 0.13 μm) .This paper supporting all of the H. 264 high profile transforms is the most efficient one, compared with the existing designs with the Data Throughput rate per Unit Area (DTUA) adopted as the comparison index.%本文针对H.264 Fidelity Range Extensions(FRExt,High Profile)解码过程中扩展的所有变换,采用二维矩阵分解和基于矩阵运算提取公共因子的操作,利用通用运算单元来设计高效的可重构VLSI结构.该结构不但节省面积(可重构变换结构只消耗了4807门电路),并且具有高性能(采用TSMC 0.13微米工艺,在150MHz的时钟频率下工作,该电路可以达到1.2G pixels/s的吞吐率,支持分辨率为4096X2048、每秒60帧的视频实时解码需求).根据OTUA(吞吐率和电路规模的比值)作为效率因子,本设计在支持H.264 High Profile所有变换的设计中具有最高的效率.
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