基于Altera浮点IP核实现浮点矩阵相乘运算时,由于矩阵阶数的增大,造成消耗的器件资源虽增加但系统性能反而下降的问题,针对现有IP核存在数据加载不连贯、存储带宽不均匀的不足,提出采用并行化数据存储、依据查找表加载数据和处理数据的方式对IP核进行改进.然后将改进的浮点矩阵运算在FPGA中实现,经过Quartus、Matlab软件联合仿真并进行结果比对,其误差不超过万分之一,且节省了器件资源、提升了系统性能.仿真结果表明该设计可行,有利于提高诸多高性能领域浮点矩阵的运算速度.%This Paper is based on the problem of increasing appliance resource consumed and decreasing systematic performance with the increasing of matrix ranks when floating IP-Core of Altera is carrying out the floating-matrix multiplication. With the aim to making up with the shortcomings of incoherent of IP-Core's data-loading and less - regularity of memory bandwidth, we take measures such as parallelizing data storage, loading and dealing with data in the LUT to improve the IP core. Then we realize the improved floating - matrix operation by FPGA, as well as emulate it by Quartus and Matlab software. Compared with the results we can find that the error is less than one ten thousandth, the appliance resource is saved off and the systematic performance is improved. The simulation investigates that the design is feasibility and it is profitable in many high-level fields.
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