An architecture-level nm-time power gating (RTPG) technique is proposed to reduce the serious active leakage power (ALP) in deep-submicron-technology circuits. The proposed scheme is built on the micro-architecture of Loogson-1 CPU and it completely depends on the accurate idle cycle prediction for execution units. According to the comparison of prediction results against the pre-characterized energy breakeven point time (EBPT) and wake-up ti/ne, the power management unit (PMU) can adaptively seize the fine-grained power gating opportunities for each power domain and wake up the sleeping power domain in advance. Experiment results on the SMIC 90nm technology node show that the active leakage power can be significantly reduced during the benchmark program execution with a moderate area overhead of 7.5 ％.%为降低深亚微米工艺集成电路的工作模式下的静态功耗,提出了一种基于功能部件空闲周期精确预测机制的结构级运行时电源门控技术.该技术通过在龙芯1号处理器体系结构的基础上构造的指令执行预测器来获得对各运算功能部件空间周期的精确预结果,并将预测结果与事先测得的运算功能部件电压域的能量损益均衡时间及唤醒时间加以比较,功耗管理单元便能够自适应地捕捉程序执行过程中各电压域细粒度的电源门控时机,同时实现对关断电压域的提前唤醒.采用SMIC 90nm工艺的实验结果表明,该技术以7.5%的处理器面积开销显著降低了运算功能部件在基准测试程序执行期间的静态功耗.
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