As more cores are integrated into one die, chip multiprocessors suffers higher on-chip communication latency, and linearly increased directory overheard. Hierarchical cache architecture partitions on-chip caches into multilevel regions recursively, reducing the communication latency by replicating the data blocks to multiple regions that contains the requestor and alleviating the storage overhead of directory by using multilevel directory. According to the data distribution in the last-level cache, we improve the data placement policy and propose an enhanced hierarchical cache directory (EHCD). EHCD directly puts an incoming off-chip data block into the lowest region that contains the requestor to reduce access latency, which guarantees only one data replica is kept in the last-level cache for private data, EHCD improves the capacity utilization of the last-level cache as well as good scalability. Simulation results on a 16-core CMP show that compared with shared organization, EHCD gets 24% execution time reduction, and 15% reduction over original hierarchical cache design.%随着片上可集成的处理器核数增加,多核处理器的片上通信延迟不断增大,目录存储开销也随之线性增长.层次化缓存结构将片上缓存递归划分为多级区域,并将数据复制到各级区域内以减小片上通信延迟,同时通过多级目录结构降低了目录存储开销.文中通过对数据访问特征进行分析,提出一种新型改进层次化缓存结构(EHCD),将从片外读入的数据直接放置在请求者所属的底层区域内,在降低延迟的同时,保证私有数据在片上最后一级缓存中只有一份副本,提高片上存储的空间利用率,具有良好的可扩展性.对16核处理器的实验结果表明,EHCD设计比传统共享缓存结构执行时间平均减少24％,比原有层次化缓存设计执行时间平均减少15％,具有很好的优化效果.
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