For modern processes at deep sub-micron technology nodes, yield design, especially the design at the layout stage is an important way to deal with the problem of manufacturability and yield. In order to reduce the yield loss caused by redundancy material defects, the choice of nets to be optimized at first is an important step in the process of layout optimization. This paper provides a new sensitivity model for a short net, which is net-based and reflects the size of the critical area between a single net and the nets around it. Since this model is based on a single net and includes the information of the surrounding nets, the critical area between the single net and surrounding nets can be reduced at the same time. In this way, the efficiency of layout optimization becomes higher. According to experimental observations, this sensitivity model can be used to choose the position for optimization. Compared with the chip-area-based and basic- layout-based sensitivity models, our sensitivity model not only has higher efficiency, but also confirms that choosing the net to be optimized at first improves the design.
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