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基于FPGA的并行RICE解码技术研究与实现

         

摘要

The RICE algorithm is widely used in the lossless compression system.Since it adopts the variable-length adaptive entropy coding,it's necessary to make bit-wise judgment and analysis in the compressed stream when decoding.However,this makes it difficult to achieve high speed decompression.Existing RICE decoding implementation methods have unsatisfactory performance in decoding speed and versatility.Given the characteristics of the adaptive entropy coding in the RICE algorithm,we propose a parallel RICE decoding structure based on finite state machine (FSM) and look up table (LUT),which can perform 8-bit width parallel decoding on the FPGA at the highest speed of 176 MB/s.And meanwhile,the decoding structure is suitable for the case where the coding parameter k is changeable,and hence it has strong versatility.%RICE算法在无损压缩系统有着广泛的应用.由于RICE算法采用了变长的自适应熵编码,因此在解码时需要对压缩流进行逐位判断和解析,这给高速解压缩的实现带来了困难.现有的RICE解码实现在解码速度和通用性上都不理想.针对RICE算法中自适应熵编码的特点,设计了一种基于有限状态机和查找表的并行RICE解码结构,可在FPGA上完成8比特宽度的并行解码,解码速度最高可达176 MB/s;同时,该解码结构适用于编码参数k变化的情况,具有很强的通用性.

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