To reduce the time overhead of assigning multiple Fast Interrupt Request(FIQ),a vectored interrupt controller for FIQ interrupt source identification and priority arbitration is designed.It is described by Verilog-HDL.Modelsim simulation and FPGA verification are also passed.Synthesis is completed with SMIC 0.13 μm CMOS technology,as well as place and route.Simulation and verification results show that the area is 0.107 mm2,the average power is 3.56 mW and the frequency is 80 MHz.This design can meet the real time demand of the chip in mobile communication RF SoC.%为降低多个中断源被分配为快速中断请求(FIQ)时的时间开销,设计一种用于FIQ中断源识别和优先级仲裁的向量中断控制器.采用Verilog语言完成硬件描述,通过Modelsim仿真和FPGA验证,实现基于SMIC0.13 μm CMOS工艺的综合布局布线工作.仿真和验证结果表明,该向量中断控制器的面积为0.107 mm2,平均功耗为3.56 mW,工作频率为80 MHz,可满足移动通信宽带射频片上系统芯片的实时性需求.
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