针对AES与SHA-3候选算法中Gr(φ)stl软件运算速度慢的问题,提出一种通过精简指令集计算机(RISC)协处理器来加速算法运算的设计方案.该协处理器复用片上高速缓存充当查找表来加速运算,并在RISC处理器的基本指令集架构中增加特殊指令.实验结果表明,与传统基于并行查找表的方案相比,该方案能够以较小的硬件代价加速AES与Gr(φ)stl运算.%Aiming at the slow operating speed of existing AES and SHA-3 candidates Grestl algorithm, this paper presents a design scheme for algorithm acceleration using Reduced Instruction Set Computer(RISC) coprocessor. Data cache is multiplexed as look-up table by the coprocessor for acceleration. Several specific instructions are added to the RISC instruction set architecture to accelerate the operation. Experimental results show that the scheme can reduce hardware cost compared with the implementation using traditional parallel on-chip look-up.
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