A Multi-bus Parallel Processor based on FPGA and Multi-DSP is designed for target identification and location. The Features can be seen as follow. The FPGA. Which controls CPLD chip via the data and control connection bus, is utilized as the data cache of the system, communication and control center. It is connected to the DSP (A), DSP (B) and DSP (C) respectively through the EMIF bus. In the aspect of control chip CPLD. The input ports are connected to the ADC and the output ports are connected to the LCD display module. Besides. FPGA generates 4 clock signals to CPLD and 3 DSP in order to synchronize the different chips. This paper improves the past single DSP to build the signal processor, with the advantages of strong function, high performance and compact structure. The system internal data transmission speed to 100M by actual testing, and can achieve maximum processing capacity of 7200 MIPS.%设计了一种用于目标识别与定位的基于FPGA和多DSP的多总线并行处理器,其特征在于将FPGA作为系统数据缓存、通信与控制中枢,以此为核心,通过数据与控制总线联接端口控制CPLD芯片,通过EMIF总线分别联接DSP (A)、DSP (B)和DSP (C)处理芯片；端口控制CPLD芯片的输入端联接多路并行ADC模数转换芯片,输出端口联接LCD输出显示模块；有源晶体振荡器与FPGA芯片联接,FPGA芯片将有源晶体振荡器分为4路时钟信号输出,分别输出到CPLD和3片DSP芯片;设计改进了传统采用单DSP搭建信号处理器模式,实际测试的系统内部数据传输速度达到100M,系统最大处理能力可以达到7200MIPS,具有功能强、性能指标高、结构紧凑的优点.
展开▼
