超大规模集成电路和超深亚微米技术的快速发展,促使了系统芯片(System on Chip,SoC)的产生,同时在SoC中也集成了越来越多的嵌入式存储器,因此嵌入式存储器对SoC芯片的整体性能有非常重要的影响;文章针对SoC中的嵌入式存储器的可测试性设计展开研究；文章基于IEEE1500标准针对DRAM和SRAM设计了具有兼容性的存储器的测试壳结构,并结合BIST控制嚣,在QuartusⅡ平台上,采用硬件描述语言对测试壳在不同测试指令下的有效性和灵活性进行验证,结果表明文章所设计的测试壳结构达到了预期的要求.%The generation of SoC (System on Chip, SoC) was prompted by the fast development of the very large scale integrated circuit and the deep sub~ micron technology. Meanwhile, more and more embedded memories are integrated in the SoC. So the reliability of the embedded memories has a very important impact on the overall performance of the SoC. This paper begins the study from the design for testability of embedded memories in the SoC. The paper designed a compatible test wrapper architecture for the SRAM and DRAM based on the IEEE 1500. In order to test the efficiency and accuracy of the test wrapper under different test instructions. Finally, simulation waveforms were got through using the hardware description language Verilog HDL on QuartusII, the results indicated that each module of wrapper was expected to reach the design requirements.
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