基于FPGA实现高清、大容量的视频处理的算法具有一定的复杂性，为了更好的用Verilog HDL描述图像处理算法，采用了一种在Simulink中搭建视频图像处理模型，利用MathWorks最新推出的Vision HDL Toolbox进行帧到像素流的转化，然后再对图像的实现边缘检测，最后把该算法自动生成Verilog HDL代码的方法，通过利用Simulink和ModelSim进行联合仿真，验证了这种方法的可行性，即可以快速的生成更加准确HDL代码，提高了用HDL描述图像处理算法的速度。%The algorithm based on FPGA to achieve high definition and large capacity video processing has certain complexity. In order to use the Verilog HDL to describe the image processing algorithms better, a set of video image processing model in Simulink is used. MathWorks company’s latest Vision HDL Toolbox is used in the conversion from frame to pixel stream, and then image edge is detected. Finally, the feasibility of the method of this algorithm automatically generating Verilog HDL is verified by using Simulink and ModelSim co-simulation. That could quickly generate more accurate HDL code, improving the speed of description of the image processing algorithm using HDL.
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