在基于机群的Mapreduce架构模型基础上,提出了一种基于CPU和FPGA环境、可扩展的Mapreduce架构.通过网络连接和驱动模块,实现了计算机软件与可编程硬件之间的通信,其中,CPU主机主要完成于文件系统的通行,将复杂耗时的运算过程转移到FPGA平台中处理,并引入内部流水线处理过程,大幅度加速了系统运算过程.同时,该架构可将更多的任务扩展到多个FPGA平台,弥补了器件内部存储资源的局限性,提高了系统的性能.此外,软硬件之间的命令、状态等信息交互为管理在FPGA中扩展任务提供了有效途径.实验证明,此架构在大幅提高运算速度的同时,提供了较好的底层设备可扩展性和管理的灵活性.%It presents a scalable Mapreduce framework on FPGA to accelerate commodity hardware. In this design,commodity hardware (CH) runs the main framework to communicate with file system in networks, while FPGA based platform is linked with CH to run Mapreduce tasks. Due to resource limited in one chip,more tasks can be extended to more FPGA platforms to achieve high-speed performance. A virtual device driver is designed in software to manage tasks running in special hardware. According to internal pipeline design and scalability, the design is proved that it allows better performance than commodity hardware, and also provides advantages in scalability and flexibility.
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