在数字滤波器中,FIR滤波器是一种结构简单且总是稳定的滤波器,同时也只有FIR滤波器拥有线性相位的特性.传统的直接型滤波器运算速度过慢,而改进型的DA结构的滤波器需要过高的芯片面积消耗大量的逻辑资源很难达到运算速度以及逻辑资源节约的整体优化.本文提出了一种基于RAG算法的FIR滤波器,与传统的基于DA算法的滤波器结构的滤波器相比,RAG算法简化了FIR滤波器乘法模块的结构,减少了逻辑资源的消耗和硬件实现面积,提高了计算速度.本文设计的16阶FIR滤波器用VerilogHDL进行描述,并综合到Altera公司的CycloneⅡ系列FPGA中.仿真实验表明基于RAG算法的FIR滤波器达到了逻辑资源的节约和运算速度的提高的整体优化效果.%In the digital filter,the FIR filter is not only a structure simple and stable filter,but also the only filter can achieve linear phase.The traditional direct-type filters' operational speed is too slow,while the improved DA structure filter needs excessive chip area,consumes logic resource and is difficult to achieve the overall optimization of the operation speed as well as logic resource conservation.An improved FIR filter based on RAG algorithm is presented in this paper.Compared with traditional DA algorithm structure filter,the RAG algorithm simplifies the multiplication module structure of FIR filter,reduces the consuming of logic resource and hardware achieving area,and increases the operational speed.This designed 16-taps FIR filter is synthesized in Altera Company's Cyclone Ⅱ FPGA written in Verilog HDL language.Simulation results show that designed FIR filter based on RAG algorithm optimizes operational speed and saves logic resource.
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