在研发一套基于0.18μm工艺的全新半导体芯片时,由于芯片工艺的要求我们将标准0.18μm工艺流程中的接触孔蚀刻阻挡层由原来的UVSIN+SION改为SIN,但却引进了PID(等离子体损伤)的问题.当芯片的关键尺寸减小到0.18μm时,栅氧化层变得更薄,对等离子体的损伤也变得更加敏感.所以如何改善PID也成为这款芯片能否成功量产的重要攻坚对象.这一失效来源于接触孔阻挡层的改变,于是将改善PID的重点放在接触孔蚀刻阻挡层之后即后段工艺上.后段的通孔蚀刻及钝化层的高密度等离子体淀积会产生较严重的等离子体损伤,因此如何改善这两步工艺以减少等离子体损伤便成为重中之重.文中通过实验验证了关闭通孔过蚀刻中的磁场以及减小钝化层的高密度等离子体淀积中的溅射刻蚀功率可以有效改善芯片的等离子体损伤.通过这两处的工艺优化,使得PID处于可控范围内,保证了量产的芯片质量.% To setup a new 0.18μm process flow for a new IC, CT stop layer was changed from UVSIN+SION to SIN. But it suffered PID (plasma induced damage) issue. When devices shrinks to 0.18μm, the gate oxide becomes thinner and it is less tolerated to plasma damage. To solve the PID issue, BEOL process was the key point and it needs to be optimized. In BEOL process, Via etch and Passivation HDP will induce highly palasma damage, so how to optimize the process is the most important. In this paper, a study of turning off the magnet when the Via over etch and reduce Passivation HDP sputter power to reduce PID is presented. By optimized the process, PID will be under the control and the chip quality will also be guaranteed.
展开▼
