According to multi rate LDPC generation matrix distribution property of DTMB standard, a high -speed LDPC encoder based on pipelined Shift Register Adder Accumulator architecture is implemented in this paper, which is serial input and serial output. This design can complete three different rate encodings. The maximum clock frequency of the whole design which is implemented on FPGA chip EP3SL150 of Ahera can be 341.88MHz. The architecture use simpler memory structure and is suitable for DTMB modulator.%针对中国数字电视广播地面传输标准（DTMB）中给出的多码率LDPC码生成矩阵的特点，设计了一种串行输入串行输出基于流水线SRAA（Shift Register Adder Accumulator）结构的编码器，并同时适用于3种不同码率的LD-PC码。在Altera公司的EP3SLl50型号FPGA平台上，整个设计最高时钟可达341．88MHz，简化了存储器设计结构，完全适合于DTMB标准调制器的开发。
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