When single Field-Programmable Gate Array (FPGA) deals with the huge amounts of data in high-speed network, low efficiency problem occurs. According to dual priority schedule algorithm for multi-processor and high-speed data acquisition and processing model based on multi-FPGA, a dual priority dynamic scheduling algorithm was proposed based on multi-FPGA. For strong real-time periodic tasks set in low priority queue, the Earliest Deadline Critical Laxity ( EDCL) scheduling algorithm was given to determine the priority of task according to the degree of relaxation of the tasks. If the task was not finished when the promotion time was up, it would be promoted to high priority queue. For soft real-time periodic tasks, an algorithm was put forward to assign the tasks to middle priority queue and schedule them by delaying the deadline of tasks to dynamic blur threshold. The experimental results show that the proposed algorithms can well schedule strong real-time periodic tasks and guarantee the priority execution of important tasks, and it can also reduce miss rate of soft real-time periodic tasks caused by preemption.%针对单片现场可编程门阵列(FPGA)在处理高速网络中海量数据时存在效率低下的问题,结合多处理器的双优先级调度算法,在所构建的多片FPGA并行处理的高速数据采集和处理模型上,提出一种基于多片FPGA的双优先级动态调度算法,并对处于低优先级段的强实时周期任务提出一种最早截止期临界松弛调度(EDCL)算法.根据任务的松弛度确定任务的优先级,若提升时间到达时仍未完成,则将其提升到高优先级段；对软实时周期任务,设置在中优先级段,通过延长当前任务截止期至动态模糊阈值进行调度.实验结果表明,该算法能很好地调度强实时周期任务,保证重要任务的优先执行,并能降低由于抢占造成的软实时周期任务错失率.
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