针对并行BCH译码器的特点,采用异或门实现有限域上常系数乘法,从而降低硬件复杂度.先计算部分错误位置多项式,再根据仿射多项式和格雷码理论,进行逻辑运算得到剩余的错误位置多项式,从而减少了系统所占用的资源.在现场可编程门阵列( FPGA)开发软件ISE10.1上进行了时序仿真,验证了该算法时间和空间的高效性.%According to the characteristics of parallel BCH decoder, the multiplication of constant coefficient in finite field was realized by using XOR gates to reduce hardware complexity. The part of the error location polynomial was calculated, and then the remaining error location polynomial could be obtained using the theory of affine polynomial and Gray code. The proposed algorithm reduces the system resources occupied. Through timing simulation on Field Programmable Gate Array (FPGA) 's development software ISE10.1, the high-efficiency of the algorithm on time and space has got verified.
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