ARCHITECTURE MODEL AND RESOURCE GRAPH BUILDING ALGORITHM FOR DETAILED FPGA ARCHITECTURE DESIGN

Li Zhihua; Yang Haigang; Yang Liqun; Li Wei; Huang Juan

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ARCHITECTURE MODEL AND RESOURCE GRAPH BUILDING ALGORITHM FOR DETAILED FPGA ARCHITECTURE DESIGN

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摘要

This paper addresses the issue of designing the detailed architectures of Field-Programmable Gate Arrays(FPGAs), which has a great impact on the overall performances of an FPGA in practice. Firstly, a novel FPGA architecture description model is proposed based on an easy-to-use file format known as YAML. This format permits the description of any detailed architecture of hard blocks and channels. Then a general algorithm of building FPGA resource graph is presented. The proposed model is scalable and capable of dealing with detailed architecture design and can be used in FPGA architecture evaluation system which is developed to enable detailed architecture design. Experimental results show that a maximum of 16.36% reduction in total wirelength and a maximum of 9.34% reduction in router effort can be obtained by making very little changes to detailed architectures, which verifies the necessity and effectiveness of the proposed model.

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来源
《电子科学学刊：英文版》 |2014年第6期|505-512|共8页
作者
Li Zhihua; Yang Haigang; Yang Liqun; Li Wei; Huang Juan;
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作者单位

University of Chinese Academy of Sciences;

System on Programmable Chip Research Department;

Institute of Electronics;

Chinese Academy of Sciences;

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原文格式 PDF
正文语种 chi
中图分类大规模集成电路、超大规模集成电路;
关键词
Field-Programmable Gate Arrays(FPGAs) architecture model; Detailed architecture design; Architecture evaluation system;

ARCHITECTURE MODEL AND RESOURCE GRAPH BUILDING ALGORITHM FOR DETAILED FPGA ARCHITECTURE DESIGN

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