In the modern analogue design, Transistor Level Fault Simulation (TLFS) plays the im-portant part since every fault in the whole circuit has to be simulated at that level. Unfortunately, it is a very CPU intensive task even though it maintains the high accuracy. Therefore, High Level Fault Modeling (HLFM) and High Level Fault Simulation (HLFS) are required in order to alleviate the efforts of simulation. In this paper, different HLFM approaches are reviewed at the device level during last two decades. We clarify their domains of application and evaluate their strengths and current limitations. We also analyze causes of faults and introduce various test approaches.
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