针对超大规模集成电路布局过程中时序优化问题,提出一种时序驱动的详细布局方法.对设计进行时序分析并获取时序违反路径集合,对路径上两个连续固定单元间的线网进行平滑处理,以减小路径曲折度以及减少线长.再针对每一个可移动单元与其相邻的线网建立二次规划时序模型,求解局部最优布局位置.对于给定的测试电路,实验结果表明,最差的时序违反与总的时序违反均有明显改善,采用ICCAD 2015竞赛的测试模板和评价方法,总的时序性能有45~350 min的提升.%To cope with the timing problem of placement in the very large integrated circuit,a timing-driven optimization method for placement was proposed.Firstly,the design was analyzed by a timing evaluation tool and the timing violation paths were collected.A rough placement method was used on the moved cells between any two successive fixed cells in those paths to smooth the nets.After that, a detailed placement based on quadratic timing model was used to optimize the timing characteristics.For the given benchmarks and the evaluation method in ICCAD 2015 contest, the experimental results show that both the worst negative slack and the total negative slack are improved, and the overall timing performance is improved by 45~350 min.
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