本文总结了由D触发器构成2n进制同步计数器的设计方法, 并在此基础上分析了如何用逻辑函数修改技术实现任意进制同步计数器．通过实例设计表明，推广此设计方法于任意进制的加、减法计数器具有使用方便、设计迅速等优点和一定的实用意义。%In this paper, the design method of an arbitrary Module-2n synchronous counters consisting of D-type flip-flops was summed up. Based upon it, some questions about how to use the logic function modification technique to achieve any module-N synchronous counters were also analyzed. The design examples show that spreading this design method to any module-N up/down counter has the advantages of being easy to use and fast to design, and is of certain practical signifiance.
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机译：f3任意参数的“ g”数字实施解码程序的加法函数结构（Σ CD ）[ 1,2 S g h1 ] f（2 n ）和[ 1,2 S g h2 ] f三元表示法f（+ 1,0，-1）和双逻辑微分d 1,2 的算术公称（2 n ）位置格式“额外代码RU” / dn→f 1,2 （ + ←↓-） d / dn “水平”活动参数2“并删除“级别1”中的活动逻辑“ +1”，“-1”→“ 0”（俄罗斯逻辑版本）
