A 22⁃bit Sigma⁃Delta modulator with high⁃accuracy third⁃order 2⁃1 cascade structure for weighing sensor ADC is presented in this paper. While the bandwidth of the input signal is 20 Hz and the oversampling ratio is 1024,Matlab/Simu⁃link mathematical modeling and simulation show that the signal⁃to⁃noise ratio(SNR)of the modulator is 170.7 dB in conside⁃ration of the nonideal factors. The circuit of the modulator is designed with Charter 0.35 μm standard CMOS process and simu⁃lated with Spectre. The result shows that the SNR can reach 144.8 dB,which is higher than 135 dB required by 22⁃bit Sigma⁃Delta modulator.% 设计一款可用于称重传感器ADC的高精度2⁃1级联结构Sigma⁃Delta调制器。在考虑非理想因素的前提下，采用Matlab/Simulink数学建模和仿真表明，在信号带宽为20 Hz，过采样率为1024的情况下，该调制器的信噪比为170.7 dB。采用Charter 0.35μm工艺对该调制器进行电路级设计并用Spectre仿真，电路信噪比为144.8 dB，该结果高于22位要求的135 dB。
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