The FPGA implementation of look-up table arithmetic-based square root raised cosine pulse shaping filter in communication system based on circuit segmentation is proposed, and how to calculate the initialization ROM data of a forming waveform is discussed. On this basis, the VHDL code and the Modelsim simulation results are elucidated. The design method is simple and easy, and is very suitable for high speed forming application.%提出了基于电路分割技术实现通信系统发送端根升余弦波形成形滤波器查表法的FPGA结构,节省了ROM单元,讨论了其ROM初始化时形波数据的组织方法,完成了该结构的VHDL实现,给出了该设计在Modelsim环境下的时序仿真结果.通过对仿真结果分析,表明所述的设计方法是可行的.该设计方案不随波形样本数目的增多而使电路系统变得更为复杂,它所实现的成形滤波器满足于高速成形的应用需求.
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