A verilog code was designed to drive a LCoS screen whose resolution is 1024 × 768. The code was synthesized and compiled in quartusⅡ9. 1 and it was implemented successfully on Altera EP3C5E144C8 and the actual output signal was measured. Asynchronous FIFO structure was adopted to solve data transmission between different clock domains. With Embedded FFT ip core, FFT transform and spectrum analysis can be done. The system provides a hardware platform for computer-generated hologram 3D image processing and display.%针对分辨率为1 024×768的LCoS屏编写了Verilog HDL驱动代码,在quartusⅡ9.1平台上综合编译,并在Altera的FPGA芯片EP3C5E144C8上进行了功能验证和实际输出信号测量.采用异步FIFO结构解决了跨异步时钟域的数据传输问题.嵌入FFT IP核后,可进一步对图像进行基于FFT的变换处理,分析图像的频谱.为计算全息3D图像处理及显示提供了硬件平台.
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