The appropriative IP core is used as the MIL-STD-1553B bus transmitter. The system and modules are designed with the top-down method The bus transmitter is programmed by VHDL language. It has been proved effective on the FPGA. The results indicate that the design which costs Less logic elements of the FPGA can meet the timing requirements of the bus standard.%为了开发具有自主产权的MIL-STD-1553B接口芯片.采用自顶向下的方法设计了一款专用的总线发送器IP核;通过自顶向下的方法完成系统设计与模块设计,使用VHDL语言书写发送器程序代码,以FPGA为平台对发送器进行了测试.结果表明,发送器的逻辑功能达到了设计要求,时序指标完全符合协议规范,实现了总线通信,具有消耗逻辑单元少的特点.
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