为提升平行板雪崩计数器（ PPAC）的使用性能，设计了一款具有50 ns和100 ns两档达峰时间的四通道滤波成形专用集成电路（ ASIC）芯片。该ASIC芯片与已有的前放芯片结合可实现PPAC的信号读出。芯片内每个通道包括极零相消、低通滤波成形及输出电路。输入动态范围－0．8～＋0．8 V内的线性度达到0．2％；－3 dB带宽噪声不高于60μV；芯片功耗30 mW；面积为2．6 mm ×1．25 mm。%This paper has introduced an application specific integrated circuit ( ASIC ) chip which has four -channel CR-RC3 shaper with 50 ns and 100 ns adjustable peaking time in order to improve the performance of Parallel plate avalanche counter ( PPAC) .The ASIC can be combined with existing pre -amplifiers for the sig-nal readout of PPAC detectors .Each channel of the ASIC includes a pole -zero cancellation circuit , a low-pass filtering and an output circuit .The linearity is achieved about 0.2%with the dynamic range from -0.8 to+0.8 V and the-3 dB bandwidth noise is not higher than 60 μV.The power dissipation of the entire chip is less than 30mW.And the chip area is 2.6 mm ×1.25 mm.
展开▼
