首页> 中文期刊> 《核技术》 >氖杂质注入条件下CFETR芯部钨杂质浓度的模拟研究

氖杂质注入条件下CFETR芯部钨杂质浓度的模拟研究

         

摘要

[Background] Due to unacceptable high erosion rate of low-Z material and the problem of tritium co-deposition, full-tungsten wall is excepted for future fusion reactor. However, the core tungsten concentration has to be limited to very low level of 10-5 due to its the high radiative cooling rate. China fusion engineering test reactor (CFETR) requires high-power steady-state operation, full tungsten wall is preferred. [Purpose] This study aims to evaluate the core tungsten concentration for CFETR with full tungsten wall. [Methods] Edge plasma simulation software scrape-off layer plasma simulation (SOLPS) is employed to simulate the edge plasma with different Ne seeding rates for the lower-single null configuration. With the simulated edge plasma as the background, Monte Carlo impurity transport code DIVertor and IMPurity (DIVIMP) is used to simulate the transportations of the impurity of tungsten. [Results] When the Ne seeding rate is low and the target temperature keeps high, the simulated core tungsten concentration is too high to be considered. The contribution of tungsten target becomes acceptable when the target temperature is lower to about 10 eV; however, when the main chamber tungsten wall is included, the core tungsten concentration is still at the level of 10-4. [Conclusion]The tungsten source from main chamber wall is the main cause of high core tungsten concentration when seeding impurity rate is high. The influence of tungsten wall on the core tungsten impurity should be further focused in future work.%由于低质量数材料不可接受的高腐蚀率以及氚共沉积的问题,未来聚变堆中更希望使用全钨壁.由于钨在芯部的高辐射冷却率,芯部的钨杂质浓度需要限制在非常低的水平(约10-5).中国聚变工程试验堆(China Fusion Engineering Test Reactor,CFETR)要求其高功率稳态运行,全钨壁是优先考虑的方案.为了估计全钨壁CFETR的芯部钨杂质浓度,用边界等离子体物理模拟软件SOLPS(Scrape-off Layer Plasma Simulation)对下单零偏滤器位形不同氖气(Ne)辐射杂质注入速率下模拟得到边界等离子体背景,再利用蒙特卡罗杂质输运程序DIVIMP(DIVertor and IMPurity)对钨杂质的输运进行了模拟.当Ne注入速率较低、靶板温度仍然较高时,即使仅考虑靶板为钨材料,芯部钨杂质浓度依然过高.当外靶板峰值温度降低至约10 eV时,钨靶板对芯部钨杂质浓度的贡献降至可接受的水平;但当包含主等离子体室壁的贡献时,芯部钨杂质浓度仍然达到10-4的水平.因此当Ne杂质注入速率较高时,过高的芯部钨杂质浓度主要来源于主等离子体室壁.未来的工作中需要进一步关注钨壁对芯部钨杂质浓度的影响.

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